ls1046a_common.h 8.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2016 Freescale Semiconductor
  4. * Copyright 2019 NXP
  5. */
  6. #ifndef __LS1046A_COMMON_H
  7. #define __LS1046A_COMMON_H
  8. /* SPL build */
  9. #ifdef CONFIG_SPL_BUILD
  10. #define SPL_NO_QBMAN
  11. #define SPL_NO_FMAN
  12. #define SPL_NO_ENV
  13. #define SPL_NO_MISC
  14. #define SPL_NO_QSPI
  15. #define SPL_NO_USB
  16. #define SPL_NO_SATA
  17. #endif
  18. #if defined(CONFIG_SPL_BUILD) && \
  19. (defined(CONFIG_NAND_BOOT) || defined(CONFIG_QSPI_BOOT))
  20. #define SPL_NO_MMC
  21. #endif
  22. #if defined(CONFIG_SPL_BUILD) && \
  23. !defined(CONFIG_SPL_FSL_LS_PPA)
  24. #define SPL_NO_IFC
  25. #endif
  26. #define CONFIG_REMAKE_ELF
  27. #define CONFIG_GICV2
  28. #include <asm/arch/config.h>
  29. #include <asm/arch/stream_id_lsch2.h>
  30. /* Link Definitions */
  31. #ifdef CONFIG_TFABOOT
  32. #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
  33. #else
  34. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
  35. #endif
  36. #define CONFIG_SKIP_LOWLEVEL_INIT
  37. #define CONFIG_VERY_BIG_RAM
  38. #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
  39. #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
  40. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  41. #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
  42. #define CPU_RELEASE_ADDR secondary_boot_func
  43. /* Generic Timer Definitions */
  44. #define COUNTER_FREQUENCY 25000000 /* 25MHz */
  45. /* Size of malloc() pool */
  46. #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
  47. /* Serial Port */
  48. #define CONFIG_SYS_NS16550_SERIAL
  49. #define CONFIG_SYS_NS16550_REG_SIZE 1
  50. #define CONFIG_SYS_NS16550_CLK (get_serial_clock())
  51. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  52. /* SD boot SPL */
  53. #ifdef CONFIG_SD_BOOT
  54. #define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */
  55. #define CONFIG_SPL_STACK 0x10020000
  56. #define CONFIG_SPL_PAD_TO 0x21000 /* 132 KiB */
  57. #define CONFIG_SPL_BSS_START_ADDR 0x8f000000
  58. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
  59. #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
  60. CONFIG_SPL_BSS_MAX_SIZE)
  61. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
  62. #ifdef CONFIG_NXP_ESBC
  63. #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
  64. /*
  65. * HDR would be appended at end of image and copied to DDR along
  66. * with U-Boot image. Here u-boot max. size is 512K. So if binary
  67. * size increases then increase this size in case of secure boot as
  68. * it uses raw u-boot image instead of fit image.
  69. */
  70. #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
  71. #else
  72. #define CONFIG_SYS_MONITOR_LEN 0x100000
  73. #endif /* ifdef CONFIG_NXP_ESBC */
  74. #endif
  75. #if defined(CONFIG_QSPI_BOOT) && defined(CONFIG_SPL)
  76. #define CONFIG_SPL_TARGET "spl/u-boot-spl.pbl"
  77. #define CONFIG_SPL_MAX_SIZE 0x1f000
  78. #define CONFIG_SPL_STACK 0x10020000
  79. #define CONFIG_SPL_PAD_TO 0x20000
  80. #define CONFIG_SPL_BSS_START_ADDR 0x8f000000
  81. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
  82. #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
  83. CONFIG_SPL_BSS_MAX_SIZE)
  84. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
  85. #define CONFIG_SYS_MONITOR_LEN 0x100000
  86. #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
  87. #endif
  88. /* NAND SPL */
  89. #ifdef CONFIG_NAND_BOOT
  90. #define CONFIG_SPL_PBL_PAD
  91. #define CONFIG_SPL_LIBCOMMON_SUPPORT
  92. #define CONFIG_SPL_LIBGENERIC_SUPPORT
  93. #define CONFIG_SPL_ENV_SUPPORT
  94. #define CONFIG_SPL_WATCHDOG_SUPPORT
  95. #define CONFIG_SPL_I2C_SUPPORT
  96. #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  97. #define CONFIG_SPL_NAND_SUPPORT
  98. #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
  99. #define CONFIG_SPL_MAX_SIZE 0x17000 /* 90 KiB */
  100. #define CONFIG_SPL_STACK 0x1001f000
  101. #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
  102. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
  103. #define CONFIG_SPL_BSS_START_ADDR 0x8f000000
  104. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
  105. #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
  106. CONFIG_SPL_BSS_MAX_SIZE)
  107. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
  108. #define CONFIG_SYS_MONITOR_LEN 0xa0000
  109. #endif
  110. /* I2C */
  111. #define CONFIG_SYS_I2C
  112. /* PCIe */
  113. #define CONFIG_PCIE1 /* PCIE controller 1 */
  114. #define CONFIG_PCIE2 /* PCIE controller 2 */
  115. #define CONFIG_PCIE3 /* PCIE controller 3 */
  116. #ifdef CONFIG_PCI
  117. #define CONFIG_PCI_SCAN_SHOW
  118. #endif
  119. /* SATA */
  120. #ifndef SPL_NO_SATA
  121. #define CONFIG_SCSI_AHCI_PLAT
  122. #define CONFIG_SYS_SATA AHCI_BASE_ADDR
  123. #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
  124. #define CONFIG_SYS_SCSI_MAX_LUN 1
  125. #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
  126. CONFIG_SYS_SCSI_MAX_LUN)
  127. #endif
  128. /* Command line configuration */
  129. /* MMC */
  130. #ifndef SPL_NO_MMC
  131. #ifdef CONFIG_MMC
  132. #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
  133. #endif
  134. #endif
  135. /* FMan ucode */
  136. #ifndef SPL_NO_FMAN
  137. #define CONFIG_SYS_DPAA_FMAN
  138. #ifdef CONFIG_SYS_DPAA_FMAN
  139. #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
  140. #endif
  141. #ifdef CONFIG_TFABOOT
  142. #define CONFIG_SYS_FMAN_FW_ADDR 0x900000
  143. #else
  144. #ifdef CONFIG_SD_BOOT
  145. /*
  146. * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  147. * about 1MB (2048 blocks), Env is stored after the image, and the env size is
  148. * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 18432(0x4800).
  149. */
  150. #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800)
  151. #elif defined(CONFIG_QSPI_BOOT)
  152. #define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
  153. #elif defined(CONFIG_NAND_BOOT)
  154. #define CONFIG_SYS_FMAN_FW_ADDR (36 * CONFIG_SYS_NAND_BLOCK_SIZE)
  155. #else
  156. #define CONFIG_SYS_FMAN_FW_ADDR 0x60900000
  157. #endif
  158. #endif
  159. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  160. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  161. #endif
  162. /* Miscellaneous configurable options */
  163. #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
  164. #define CONFIG_HWCONFIG
  165. #define HWCONFIG_BUFFER_SIZE 128
  166. #ifndef CONFIG_SPL_BUILD
  167. #define BOOT_TARGET_DEVICES(func) \
  168. func(SCSI, scsi, 0) \
  169. func(MMC, mmc, 0) \
  170. func(USB, usb, 0) \
  171. func(DHCP, dhcp, na)
  172. #include <config_distro_bootcmd.h>
  173. #endif
  174. #if defined(CONFIG_TARGET_LS1046AFRWY)
  175. #define LS1046A_BOOT_SRC_AND_HDR\
  176. "boot_scripts=ls1046afrwy_boot.scr\0" \
  177. "boot_script_hdr=hdr_ls1046afrwy_bs.out\0"
  178. #else
  179. #define LS1046A_BOOT_SRC_AND_HDR\
  180. "boot_scripts=ls1046ardb_boot.scr\0" \
  181. "boot_script_hdr=hdr_ls1046ardb_bs.out\0"
  182. #endif
  183. #ifndef SPL_NO_MISC
  184. /* Initial environment variables */
  185. #define CONFIG_EXTRA_ENV_SETTINGS \
  186. "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  187. "ramdisk_addr=0x800000\0" \
  188. "ramdisk_size=0x2000000\0" \
  189. "fdt_high=0xffffffffffffffff\0" \
  190. "initrd_high=0xffffffffffffffff\0" \
  191. "fdt_addr=0x64f00000\0" \
  192. "kernel_addr=0x65000000\0" \
  193. "scriptaddr=0x80000000\0" \
  194. "scripthdraddr=0x80080000\0" \
  195. "fdtheader_addr_r=0x80100000\0" \
  196. "kernelheader_addr_r=0x80200000\0" \
  197. "load_addr=0xa0000000\0" \
  198. "kernel_addr_r=0x81000000\0" \
  199. "fdt_addr_r=0x90000000\0" \
  200. "ramdisk_addr_r=0xa0000000\0" \
  201. "kernel_start=0x1000000\0" \
  202. "kernelheader_start=0x800000\0" \
  203. "kernel_load=0xa0000000\0" \
  204. "kernel_size=0x2800000\0" \
  205. "kernelheader_size=0x40000\0" \
  206. "kernel_addr_sd=0x8000\0" \
  207. "kernel_size_sd=0x14000\0" \
  208. "kernelhdr_addr_sd=0x4000\0" \
  209. "kernelhdr_size_sd=0x10\0" \
  210. "console=ttyS0,115200\0" \
  211. CONFIG_MTDPARTS_DEFAULT "\0" \
  212. BOOTENV \
  213. LS1046A_BOOT_SRC_AND_HDR \
  214. "scan_dev_for_boot_part=" \
  215. "part list ${devtype} ${devnum} devplist; " \
  216. "env exists devplist || setenv devplist 1; " \
  217. "for distro_bootpart in ${devplist}; do " \
  218. "if fstype ${devtype} " \
  219. "${devnum}:${distro_bootpart} " \
  220. "bootfstype; then " \
  221. "run scan_dev_for_boot; " \
  222. "fi; " \
  223. "done\0" \
  224. "boot_a_script=" \
  225. "load ${devtype} ${devnum}:${distro_bootpart} " \
  226. "${scriptaddr} ${prefix}${script}; " \
  227. "env exists secureboot && load ${devtype} " \
  228. "${devnum}:${distro_bootpart} " \
  229. "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
  230. "env exists secureboot " \
  231. "&& esbc_validate ${scripthdraddr};" \
  232. "source ${scriptaddr}\0" \
  233. "qspi_bootcmd=echo Trying load from qspi..;" \
  234. "sf probe && sf read $load_addr " \
  235. "$kernel_start $kernel_size; env exists secureboot " \
  236. "&& sf read $kernelheader_addr_r $kernelheader_start " \
  237. "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
  238. "bootm $load_addr#$board\0" \
  239. "sd_bootcmd=echo Trying load from SD ..;" \
  240. "mmcinfo; mmc read $load_addr " \
  241. "$kernel_addr_sd $kernel_size_sd && " \
  242. "env exists secureboot && mmc read $kernelheader_addr_r " \
  243. "$kernelhdr_addr_sd $kernelhdr_size_sd " \
  244. " && esbc_validate ${kernelheader_addr_r};" \
  245. "bootm $load_addr#$board\0"
  246. #endif
  247. /* Monitor Command Prompt */
  248. #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
  249. #define CONFIG_SYS_MAXARGS 64 /* max command args */
  250. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  251. #include <asm/arch/soc.h>
  252. #endif /* __LS1046A_COMMON_H */