ls1043ardb.h 9.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2015 Freescale Semiconductor
  4. */
  5. #ifndef __LS1043ARDB_H__
  6. #define __LS1043ARDB_H__
  7. #include "ls1043a_common.h"
  8. #define CONFIG_SYS_CLK_FREQ 100000000
  9. #define CONFIG_DDR_CLK_FREQ 100000000
  10. #define CONFIG_LAYERSCAPE_NS_ACCESS
  11. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  12. /* Physical Memory Map */
  13. #define CONFIG_CHIP_SELECTS_PER_CTRL 4
  14. #define CONFIG_SYS_SPD_BUS_NUM 0
  15. #ifndef CONFIG_SPL
  16. #define CONFIG_SYS_DDR_RAW_TIMING
  17. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  18. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  19. #endif
  20. #ifdef CONFIG_RAMBOOT_PBL
  21. #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
  22. #endif
  23. #ifdef CONFIG_NAND_BOOT
  24. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
  25. #endif
  26. #ifdef CONFIG_SD_BOOT
  27. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
  28. #define CONFIG_CMD_SPL
  29. #define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000
  30. #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x10000
  31. #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x500
  32. #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 30
  33. #endif
  34. /*
  35. * NOR Flash Definitions
  36. */
  37. #define CONFIG_SYS_NOR_CSPR_EXT (0x0)
  38. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  39. #define CONFIG_SYS_NOR_CSPR \
  40. (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  41. CSPR_PORT_SIZE_16 | \
  42. CSPR_MSEL_NOR | \
  43. CSPR_V)
  44. /* NOR Flash Timing Params */
  45. #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
  46. CSOR_NOR_TRHZ_80)
  47. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
  48. FTIM0_NOR_TEADC(0x1) | \
  49. FTIM0_NOR_TAVDS(0x0) | \
  50. FTIM0_NOR_TEAHC(0xc))
  51. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1c) | \
  52. FTIM1_NOR_TRAD_NOR(0xb) | \
  53. FTIM1_NOR_TSEQRAD_NOR(0x9))
  54. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \
  55. FTIM2_NOR_TCH(0x4) | \
  56. FTIM2_NOR_TWPH(0x8) | \
  57. FTIM2_NOR_TWP(0x10))
  58. #define CONFIG_SYS_NOR_FTIM3 0
  59. #define CONFIG_SYS_IFC_CCR 0x01000000
  60. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  61. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  62. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  63. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  64. #define CONFIG_SYS_FLASH_EMPTY_INFO
  65. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
  66. #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
  67. #define CONFIG_SYS_WRITE_SWAPPED_DATA
  68. /*
  69. * NAND Flash Definitions
  70. */
  71. #ifndef SPL_NO_IFC
  72. #define CONFIG_NAND_FSL_IFC
  73. #endif
  74. #define CONFIG_SYS_NAND_BASE 0x7e800000
  75. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  76. #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
  77. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  78. | CSPR_PORT_SIZE_8 \
  79. | CSPR_MSEL_NAND \
  80. | CSPR_V)
  81. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  82. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  83. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  84. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  85. | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
  86. | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
  87. | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
  88. | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
  89. #define CONFIG_SYS_NAND_ONFI_DETECTION
  90. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
  91. FTIM0_NAND_TWP(0x18) | \
  92. FTIM0_NAND_TWCHT(0x7) | \
  93. FTIM0_NAND_TWH(0xa))
  94. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  95. FTIM1_NAND_TWBE(0x39) | \
  96. FTIM1_NAND_TRR(0xe) | \
  97. FTIM1_NAND_TRP(0x18))
  98. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
  99. FTIM2_NAND_TREH(0xa) | \
  100. FTIM2_NAND_TWHRE(0x1e))
  101. #define CONFIG_SYS_NAND_FTIM3 0x0
  102. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  103. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  104. #define CONFIG_MTD_NAND_VERIFY_WRITE
  105. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  106. #ifdef CONFIG_NAND_BOOT
  107. #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
  108. #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
  109. #define CONFIG_SYS_NAND_U_BOOT_SIZE (1024 << 10)
  110. #endif
  111. /*
  112. * CPLD
  113. */
  114. #define CONFIG_SYS_CPLD_BASE 0x7fb00000
  115. #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
  116. #define CONFIG_SYS_CPLD_CSPR_EXT (0x0)
  117. #define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
  118. CSPR_PORT_SIZE_8 | \
  119. CSPR_MSEL_GPCM | \
  120. CSPR_V)
  121. #define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024)
  122. #define CONFIG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
  123. CSOR_NOR_NOR_MODE_AVD_NOR | \
  124. CSOR_NOR_TRHZ_80)
  125. /* CPLD Timing parameters for IFC GPCM */
  126. #define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
  127. FTIM0_GPCM_TEADC(0xf) | \
  128. FTIM0_GPCM_TEAHC(0xf))
  129. #define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
  130. FTIM1_GPCM_TRAD(0x3f))
  131. #define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
  132. FTIM2_GPCM_TCH(0xf) | \
  133. FTIM2_GPCM_TWP(0xff))
  134. #define CONFIG_SYS_CPLD_FTIM3 0x0
  135. /* IFC Timing Params */
  136. #ifdef CONFIG_TFABOOT
  137. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
  138. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
  139. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  140. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  141. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  142. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  143. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  144. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  145. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
  146. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
  147. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
  148. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
  149. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
  150. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
  151. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
  152. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
  153. #else
  154. #ifdef CONFIG_NAND_BOOT
  155. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  156. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  157. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  158. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  159. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  160. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  161. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  162. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  163. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
  164. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
  165. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  166. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  167. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  168. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  169. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  170. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  171. #else
  172. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
  173. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
  174. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  175. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  176. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  177. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  178. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  179. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  180. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
  181. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
  182. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
  183. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
  184. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
  185. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
  186. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
  187. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
  188. #endif
  189. #endif
  190. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT
  191. #define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR
  192. #define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK
  193. #define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR
  194. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0
  195. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1
  196. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2
  197. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3
  198. /* EEPROM */
  199. #ifndef SPL_NO_EEPROM
  200. #define CONFIG_ID_EEPROM
  201. #define CONFIG_SYS_I2C_EEPROM_NXID
  202. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  203. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
  204. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  205. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  206. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  207. #endif
  208. /*
  209. * Environment
  210. */
  211. #ifndef SPL_NO_ENV
  212. #define CONFIG_ENV_OVERWRITE
  213. #endif
  214. #ifdef CONFIG_TFABOOT
  215. #define CONFIG_SYS_MMC_ENV_DEV 0
  216. #else
  217. #if defined(CONFIG_NAND_BOOT)
  218. #elif defined(CONFIG_SD_BOOT)
  219. #define CONFIG_SYS_MMC_ENV_DEV 0
  220. #endif
  221. #endif
  222. /* FMan */
  223. #ifndef SPL_NO_FMAN
  224. #define AQR105_IRQ_MASK 0x40000000
  225. #ifdef CONFIG_NET
  226. #define CONFIG_PHY_VITESSE
  227. #define CONFIG_PHY_REALTEK
  228. #endif
  229. #ifdef CONFIG_SYS_DPAA_FMAN
  230. #define RGMII_PHY1_ADDR 0x1
  231. #define RGMII_PHY2_ADDR 0x2
  232. #define QSGMII_PORT1_PHY_ADDR 0x4
  233. #define QSGMII_PORT2_PHY_ADDR 0x5
  234. #define QSGMII_PORT3_PHY_ADDR 0x6
  235. #define QSGMII_PORT4_PHY_ADDR 0x7
  236. #define FM1_10GEC1_PHY_ADDR 0x1
  237. #define CONFIG_ETHPRIME "FM1@DTSEC3"
  238. #endif
  239. #endif
  240. /* SATA */
  241. #ifndef SPL_NO_SATA
  242. #ifndef CONFIG_CMD_EXT2
  243. #define CONFIG_CMD_EXT2
  244. #endif
  245. #define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
  246. #define CONFIG_SYS_SCSI_MAX_LUN 2
  247. #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
  248. CONFIG_SYS_SCSI_MAX_LUN)
  249. #define SCSI_VEND_ID 0x1b4b
  250. #define SCSI_DEV_ID 0x9170
  251. #define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
  252. #endif
  253. #include <asm/fsl_secure_boot.h>
  254. #endif /* __LS1043ARDB_H__ */