ls1043a_common.h 10 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2015 Freescale Semiconductor
  4. */
  5. #ifndef __LS1043A_COMMON_H
  6. #define __LS1043A_COMMON_H
  7. /* SPL build */
  8. #ifdef CONFIG_SPL_BUILD
  9. #define SPL_NO_FMAN
  10. #define SPL_NO_DSPI
  11. #define SPL_NO_PCIE
  12. #define SPL_NO_ENV
  13. #define SPL_NO_MISC
  14. #define SPL_NO_USB
  15. #define SPL_NO_SATA
  16. #define SPL_NO_QE
  17. #define SPL_NO_EEPROM
  18. #endif
  19. #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
  20. #define SPL_NO_MMC
  21. #endif
  22. #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI))
  23. #define SPL_NO_IFC
  24. #endif
  25. #define CONFIG_REMAKE_ELF
  26. #define CONFIG_GICV2
  27. #include <asm/arch/stream_id_lsch2.h>
  28. #include <asm/arch/config.h>
  29. /* Link Definitions */
  30. #ifdef CONFIG_TFABOOT
  31. #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
  32. #else
  33. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
  34. #endif
  35. #define CONFIG_SKIP_LOWLEVEL_INIT
  36. #define CONFIG_VERY_BIG_RAM
  37. #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
  38. #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
  39. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  40. #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
  41. #define CPU_RELEASE_ADDR secondary_boot_func
  42. /* Generic Timer Definitions */
  43. #define COUNTER_FREQUENCY 25000000 /* 25MHz */
  44. /* Size of malloc() pool */
  45. #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
  46. /* Serial Port */
  47. #define CONFIG_SYS_NS16550_SERIAL
  48. #define CONFIG_SYS_NS16550_REG_SIZE 1
  49. #define CONFIG_SYS_NS16550_CLK (get_serial_clock())
  50. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  51. /* SD boot SPL */
  52. #ifdef CONFIG_SD_BOOT
  53. #define CONFIG_SPL_MAX_SIZE 0x17000
  54. #define CONFIG_SPL_STACK 0x1001e000
  55. #define CONFIG_SPL_PAD_TO 0x1d000
  56. #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
  57. CONFIG_SPL_BSS_MAX_SIZE)
  58. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
  59. #define CONFIG_SPL_BSS_START_ADDR 0x8f000000
  60. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
  61. #ifdef CONFIG_NXP_ESBC
  62. #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
  63. /*
  64. * HDR would be appended at end of image and copied to DDR along
  65. * with U-Boot image. Here u-boot max. size is 512K. So if binary
  66. * size increases then increase this size in case of secure boot as
  67. * it uses raw u-boot image instead of fit image.
  68. */
  69. #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
  70. #else
  71. #define CONFIG_SYS_MONITOR_LEN 0x100000
  72. #endif /* ifdef CONFIG_NXP_ESBC */
  73. #endif
  74. /* NAND SPL */
  75. #ifdef CONFIG_NAND_BOOT
  76. #define CONFIG_SPL_PBL_PAD
  77. #define CONFIG_SPL_MAX_SIZE 0x1a000
  78. #define CONFIG_SPL_STACK 0x1001d000
  79. #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
  80. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
  81. #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
  82. #define CONFIG_SPL_BSS_START_ADDR 0x80100000
  83. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
  84. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
  85. #ifdef CONFIG_NXP_ESBC
  86. #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
  87. #endif /* ifdef CONFIG_NXP_ESBC */
  88. #ifdef CONFIG_U_BOOT_HDR_SIZE
  89. /*
  90. * HDR would be appended at end of image and copied to DDR along
  91. * with U-Boot image. Here u-boot max. size is 512K. So if binary
  92. * size increases then increase this size in case of secure boot as
  93. * it uses raw u-boot image instead of fit image.
  94. */
  95. #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
  96. #else
  97. #define CONFIG_SYS_MONITOR_LEN 0x100000
  98. #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
  99. #endif
  100. /* IFC */
  101. #ifndef SPL_NO_IFC
  102. #if defined(CONFIG_TFABOOT) || \
  103. (!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI))
  104. #define CONFIG_FSL_IFC
  105. /*
  106. * CONFIG_SYS_FLASH_BASE has the final address (core view)
  107. * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
  108. * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
  109. * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
  110. */
  111. #define CONFIG_SYS_FLASH_BASE 0x60000000
  112. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  113. #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
  114. #ifdef CONFIG_MTD_NOR_FLASH
  115. #define CONFIG_SYS_FLASH_QUIET_TEST
  116. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  117. #endif
  118. #endif
  119. #endif
  120. /* I2C */
  121. #define CONFIG_SYS_I2C
  122. /* PCIe */
  123. #ifndef SPL_NO_PCIE
  124. #define CONFIG_PCIE1 /* PCIE controller 1 */
  125. #define CONFIG_PCIE2 /* PCIE controller 2 */
  126. #define CONFIG_PCIE3 /* PCIE controller 3 */
  127. #ifdef CONFIG_PCI
  128. #define CONFIG_PCI_SCAN_SHOW
  129. #endif
  130. #endif
  131. /* Command line configuration */
  132. /* MMC */
  133. #ifndef SPL_NO_MMC
  134. #ifdef CONFIG_MMC
  135. #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
  136. #endif
  137. #endif
  138. /* DSPI */
  139. #ifndef SPL_NO_DSPI
  140. #define CONFIG_FSL_DSPI
  141. #ifdef CONFIG_FSL_DSPI
  142. #define CONFIG_DM_SPI_FLASH
  143. #define CONFIG_SPI_FLASH_STMICRO /* cs0 */
  144. #define CONFIG_SPI_FLASH_SST /* cs1 */
  145. #define CONFIG_SPI_FLASH_EON /* cs2 */
  146. #endif
  147. #endif
  148. /* FMan ucode */
  149. #ifndef SPL_NO_FMAN
  150. #define CONFIG_SYS_DPAA_FMAN
  151. #ifdef CONFIG_SYS_DPAA_FMAN
  152. #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
  153. #ifdef CONFIG_TFABOOT
  154. #define CONFIG_SYS_FMAN_FW_ADDR 0x900000
  155. #define CONFIG_SYS_QE_FW_ADDR 0x940000
  156. #else
  157. #ifdef CONFIG_NAND_BOOT
  158. /* Store Fman ucode at offeset 0x900000(72 blocks). */
  159. #define CONFIG_SYS_FMAN_FW_ADDR (72 * CONFIG_SYS_NAND_BLOCK_SIZE)
  160. #elif defined(CONFIG_SD_BOOT)
  161. /*
  162. * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  163. * about 1MB (2040 blocks), Env is stored after the image, and the env size is
  164. * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 18432(0x4800).
  165. */
  166. #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800)
  167. #define CONFIG_SYS_QE_FW_ADDR (512 * 0x4A00)
  168. #elif defined(CONFIG_QSPI_BOOT)
  169. #define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
  170. #else
  171. /* FMan fireware Pre-load address */
  172. #define CONFIG_SYS_FMAN_FW_ADDR 0x60900000
  173. #define CONFIG_SYS_QE_FW_ADDR 0x60940000
  174. #endif
  175. #endif
  176. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  177. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  178. #endif
  179. #endif
  180. /* Miscellaneous configurable options */
  181. #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
  182. #define CONFIG_HWCONFIG
  183. #define HWCONFIG_BUFFER_SIZE 128
  184. #ifndef SPL_NO_MISC
  185. #ifndef CONFIG_SPL_BUILD
  186. #define BOOT_TARGET_DEVICES(func) \
  187. func(MMC, mmc, 0) \
  188. func(USB, usb, 0) \
  189. func(DHCP, dhcp, na)
  190. #include <config_distro_bootcmd.h>
  191. #endif
  192. /* Initial environment variables */
  193. #define CONFIG_EXTRA_ENV_SETTINGS \
  194. "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  195. "fdt_high=0xffffffffffffffff\0" \
  196. "initrd_high=0xffffffffffffffff\0" \
  197. "fdt_addr=0x64f00000\0" \
  198. "kernel_addr=0x61000000\0" \
  199. "scriptaddr=0x80000000\0" \
  200. "scripthdraddr=0x80080000\0" \
  201. "fdtheader_addr_r=0x80100000\0" \
  202. "kernelheader_addr_r=0x80200000\0" \
  203. "kernel_addr_r=0x81000000\0" \
  204. "kernel_start=0x1000000\0" \
  205. "kernelheader_start=0x800000\0" \
  206. "fdt_addr_r=0x90000000\0" \
  207. "load_addr=0xa0000000\0" \
  208. "kernelheader_addr=0x60800000\0" \
  209. "kernel_size=0x2800000\0" \
  210. "kernelheader_size=0x40000\0" \
  211. "kernel_addr_sd=0x8000\0" \
  212. "kernel_size_sd=0x14000\0" \
  213. "kernelhdr_addr_sd=0x4000\0" \
  214. "kernelhdr_size_sd=0x10\0" \
  215. "console=ttyS0,115200\0" \
  216. "boot_os=y\0" \
  217. "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
  218. BOOTENV \
  219. "boot_scripts=ls1043ardb_boot.scr\0" \
  220. "boot_script_hdr=hdr_ls1043ardb_bs.out\0" \
  221. "scan_dev_for_boot_part=" \
  222. "part list ${devtype} ${devnum} devplist; " \
  223. "env exists devplist || setenv devplist 1; " \
  224. "for distro_bootpart in ${devplist}; do " \
  225. "if fstype ${devtype} " \
  226. "${devnum}:${distro_bootpart} " \
  227. "bootfstype; then " \
  228. "run scan_dev_for_boot; " \
  229. "fi; " \
  230. "done\0" \
  231. "boot_a_script=" \
  232. "load ${devtype} ${devnum}:${distro_bootpart} " \
  233. "${scriptaddr} ${prefix}${script}; " \
  234. "env exists secureboot && load ${devtype} " \
  235. "${devnum}:${distro_bootpart} " \
  236. "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
  237. "env exists secureboot " \
  238. "&& esbc_validate ${scripthdraddr};" \
  239. "source ${scriptaddr}\0" \
  240. "qspi_bootcmd=echo Trying load from qspi..;" \
  241. "sf probe && sf read $load_addr " \
  242. "$kernel_start $kernel_size; env exists secureboot " \
  243. "&& sf read $kernelheader_addr_r $kernelheader_start " \
  244. "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
  245. "bootm $load_addr#$board\0" \
  246. "nor_bootcmd=echo Trying load from nor..;" \
  247. "cp.b $kernel_addr $load_addr " \
  248. "$kernel_size; env exists secureboot " \
  249. "&& cp.b $kernelheader_addr $kernelheader_addr_r " \
  250. "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
  251. "bootm $load_addr#$board\0" \
  252. "nand_bootcmd=echo Trying load from NAND..;" \
  253. "nand info; nand read $load_addr " \
  254. "$kernel_start $kernel_size; env exists secureboot " \
  255. "&& nand read $kernelheader_addr_r $kernelheader_start " \
  256. "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
  257. "bootm $load_addr#$board\0" \
  258. "sd_bootcmd=echo Trying load from SD ..;" \
  259. "mmcinfo; mmc read $load_addr " \
  260. "$kernel_addr_sd $kernel_size_sd && " \
  261. "env exists secureboot && mmc read $kernelheader_addr_r " \
  262. "$kernelhdr_addr_sd $kernelhdr_size_sd " \
  263. " && esbc_validate ${kernelheader_addr_r};" \
  264. "bootm $load_addr#$board\0"
  265. #undef CONFIG_BOOTCOMMAND
  266. #ifdef CONFIG_TFABOOT
  267. #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
  268. "env exists secureboot && esbc_halt;"
  269. #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
  270. "env exists secureboot && esbc_halt;"
  271. #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
  272. "env exists secureboot && esbc_halt;"
  273. #define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; " \
  274. "env exists secureboot && esbc_halt;"
  275. #else
  276. #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  277. #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
  278. "env exists secureboot && esbc_halt;"
  279. #elif defined(CONFIG_SD_BOOT)
  280. #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
  281. "env exists secureboot && esbc_halt;"
  282. #else
  283. #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
  284. "env exists secureboot && esbc_halt;"
  285. #endif
  286. #endif
  287. #endif
  288. /* Monitor Command Prompt */
  289. #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
  290. #define CONFIG_SYS_MAXARGS 64 /* max command args */
  291. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  292. #include <asm/arch/soc.h>
  293. #endif /* __LS1043A_COMMON_H */