ls1021atwr.h 14 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef __CONFIG_H
  6. #define __CONFIG_H
  7. #define CONFIG_ARMV7_PSCI_1_0
  8. #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
  9. #define CONFIG_SYS_FSL_CLK
  10. #define CONFIG_SKIP_LOWLEVEL_INIT
  11. #define CONFIG_DEEP_SLEEP
  12. /*
  13. * Size of malloc() pool
  14. */
  15. #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
  16. #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
  17. #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
  18. #define CONFIG_SYS_CLK_FREQ 100000000
  19. #define CONFIG_DDR_CLK_FREQ 100000000
  20. #define DDR_SDRAM_CFG 0x470c0008
  21. #define DDR_CS0_BNDS 0x008000bf
  22. #define DDR_CS0_CONFIG 0x80014302
  23. #define DDR_TIMING_CFG_0 0x50550004
  24. #define DDR_TIMING_CFG_1 0xbcb38c56
  25. #define DDR_TIMING_CFG_2 0x0040d120
  26. #define DDR_TIMING_CFG_3 0x010e1000
  27. #define DDR_TIMING_CFG_4 0x00000001
  28. #define DDR_TIMING_CFG_5 0x03401400
  29. #define DDR_SDRAM_CFG_2 0x00401010
  30. #define DDR_SDRAM_MODE 0x00061c60
  31. #define DDR_SDRAM_MODE_2 0x00180000
  32. #define DDR_SDRAM_INTERVAL 0x18600618
  33. #define DDR_DDR_WRLVL_CNTL 0x8655f605
  34. #define DDR_DDR_WRLVL_CNTL_2 0x05060607
  35. #define DDR_DDR_WRLVL_CNTL_3 0x05050505
  36. #define DDR_DDR_CDR1 0x80040000
  37. #define DDR_DDR_CDR2 0x00000001
  38. #define DDR_SDRAM_CLK_CNTL 0x02000000
  39. #define DDR_DDR_ZQ_CNTL 0x89080600
  40. #define DDR_CS0_CONFIG_2 0
  41. #define DDR_SDRAM_CFG_MEM_EN 0x80000000
  42. #define SDRAM_CFG2_D_INIT 0x00000010
  43. #define DDR_CDR2_VREF_TRAIN_EN 0x00000080
  44. #define SDRAM_CFG2_FRC_SR 0x80000000
  45. #define SDRAM_CFG_BI 0x00000001
  46. #ifdef CONFIG_RAMBOOT_PBL
  47. #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg
  48. #endif
  49. #ifdef CONFIG_SD_BOOT
  50. #ifdef CONFIG_SD_BOOT_QSPI
  51. #define CONFIG_SYS_FSL_PBL_RCW \
  52. board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
  53. #else
  54. #define CONFIG_SYS_FSL_PBL_RCW \
  55. board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
  56. #endif
  57. #ifdef CONFIG_NXP_ESBC
  58. /*
  59. * HDR would be appended at end of image and copied to DDR along
  60. * with U-Boot image.
  61. */
  62. #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
  63. #endif /* ifdef CONFIG_NXP_ESBC */
  64. #define CONFIG_SPL_MAX_SIZE 0x1a000
  65. #define CONFIG_SPL_STACK 0x1001d000
  66. #define CONFIG_SPL_PAD_TO 0x1c000
  67. #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
  68. CONFIG_SYS_MONITOR_LEN)
  69. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
  70. #define CONFIG_SPL_BSS_START_ADDR 0x80100000
  71. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
  72. #ifdef CONFIG_U_BOOT_HDR_SIZE
  73. /*
  74. * HDR would be appended at end of image and copied to DDR along
  75. * with U-Boot image. Here u-boot max. size is 512K. So if binary
  76. * size increases then increase this size in case of secure boot as
  77. * it uses raw u-boot image instead of fit image.
  78. */
  79. #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
  80. #else
  81. #define CONFIG_SYS_MONITOR_LEN 0x100000
  82. #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
  83. #endif
  84. #define PHYS_SDRAM 0x80000000
  85. #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
  86. #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
  87. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  88. #define CONFIG_CHIP_SELECTS_PER_CTRL 4
  89. /*
  90. * IFC Definitions
  91. */
  92. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  93. #define CONFIG_FSL_IFC
  94. #define CONFIG_SYS_FLASH_BASE 0x60000000
  95. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  96. #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
  97. #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  98. CSPR_PORT_SIZE_16 | \
  99. CSPR_MSEL_NOR | \
  100. CSPR_V)
  101. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
  102. /* NOR Flash Timing Params */
  103. #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
  104. CSOR_NOR_TRHZ_80)
  105. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  106. FTIM0_NOR_TEADC(0x5) | \
  107. FTIM0_NOR_TAVDS(0x0) | \
  108. FTIM0_NOR_TEAHC(0x5))
  109. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  110. FTIM1_NOR_TRAD_NOR(0x1A) | \
  111. FTIM1_NOR_TSEQRAD_NOR(0x13))
  112. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  113. FTIM2_NOR_TCH(0x4) | \
  114. FTIM2_NOR_TWP(0x1c) | \
  115. FTIM2_NOR_TWPH(0x0e))
  116. #define CONFIG_SYS_NOR_FTIM3 0
  117. #define CONFIG_SYS_FLASH_QUIET_TEST
  118. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  119. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  120. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  121. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  122. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  123. #define CONFIG_SYS_FLASH_EMPTY_INFO
  124. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
  125. #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
  126. #define CONFIG_SYS_WRITE_SWAPPED_DATA
  127. #endif
  128. /* CPLD */
  129. #define CONFIG_SYS_CPLD_BASE 0x7fb00000
  130. #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
  131. #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
  132. #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
  133. CSPR_PORT_SIZE_8 | \
  134. CSPR_MSEL_GPCM | \
  135. CSPR_V)
  136. #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
  137. #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
  138. CSOR_NOR_NOR_MODE_AVD_NOR | \
  139. CSOR_NOR_TRHZ_80)
  140. /* CPLD Timing parameters for IFC GPCM */
  141. #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
  142. FTIM0_GPCM_TEADC(0xf) | \
  143. FTIM0_GPCM_TEAHC(0xf))
  144. #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
  145. FTIM1_GPCM_TRAD(0x3f))
  146. #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
  147. FTIM2_GPCM_TCH(0xf) | \
  148. FTIM2_GPCM_TWP(0xff))
  149. #define CONFIG_SYS_FPGA_FTIM3 0x0
  150. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  151. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
  152. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  153. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  154. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  155. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  156. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  157. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  158. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT
  159. #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR
  160. #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK
  161. #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR
  162. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0
  163. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1
  164. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2
  165. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3
  166. /*
  167. * Serial Port
  168. */
  169. #ifdef CONFIG_LPUART
  170. #define CONFIG_LPUART_32B_REG
  171. #else
  172. #define CONFIG_SYS_NS16550_SERIAL
  173. #ifndef CONFIG_DM_SERIAL
  174. #define CONFIG_SYS_NS16550_REG_SIZE 1
  175. #endif
  176. #define CONFIG_SYS_NS16550_CLK get_serial_clock()
  177. #endif
  178. /*
  179. * I2C
  180. */
  181. #define CONFIG_SYS_I2C
  182. #define CONFIG_SYS_I2C_MXC
  183. #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
  184. #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
  185. #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
  186. /* EEPROM */
  187. #define CONFIG_ID_EEPROM
  188. #define CONFIG_SYS_I2C_EEPROM_NXID
  189. #define CONFIG_SYS_EEPROM_BUS_NUM 1
  190. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
  191. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  192. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  193. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  194. /*
  195. * MMC
  196. */
  197. /* SPI */
  198. #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  199. /* QSPI */
  200. #define QSPI0_AMBA_BASE 0x40000000
  201. #define FSL_QSPI_FLASH_SIZE (1 << 24)
  202. #define FSL_QSPI_FLASH_NUM 2
  203. /* DSPI */
  204. #endif
  205. /* DM SPI */
  206. #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
  207. #define CONFIG_DM_SPI_FLASH
  208. #endif
  209. /*
  210. * Video
  211. */
  212. #ifdef CONFIG_VIDEO_FSL_DCU_FB
  213. #define CONFIG_VIDEO_LOGO
  214. #define CONFIG_VIDEO_BMP_LOGO
  215. #define CONFIG_FSL_DCU_SII9022A
  216. #define CONFIG_SYS_I2C_DVI_BUS_NUM 1
  217. #define CONFIG_SYS_I2C_DVI_ADDR 0x39
  218. #endif
  219. /*
  220. * eTSEC
  221. */
  222. #ifdef CONFIG_TSEC_ENET
  223. #define CONFIG_ETHPRIME "ethernet@2d10000"
  224. #endif
  225. /* PCIe */
  226. #define CONFIG_PCIE1 /* PCIE controller 1 */
  227. #define CONFIG_PCIE2 /* PCIE controller 2 */
  228. #ifdef CONFIG_PCI
  229. #define CONFIG_PCI_SCAN_SHOW
  230. #endif
  231. #define CONFIG_CMDLINE_TAG
  232. #define CONFIG_PEN_ADDR_BIG_ENDIAN
  233. #define CONFIG_LAYERSCAPE_NS_ACCESS
  234. #define CONFIG_SMP_PEN_ADDR 0x01ee0200
  235. #define COUNTER_FREQUENCY 12500000
  236. #define CONFIG_HWCONFIG
  237. #define HWCONFIG_BUFFER_SIZE 256
  238. #define CONFIG_FSL_DEVICE_DISABLE
  239. #define BOOT_TARGET_DEVICES(func) \
  240. func(MMC, mmc, 0) \
  241. func(USB, usb, 0) \
  242. func(DHCP, dhcp, na)
  243. #include <config_distro_bootcmd.h>
  244. #ifdef CONFIG_LPUART
  245. #define CONFIG_EXTRA_ENV_SETTINGS \
  246. "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
  247. "initrd_high=0xffffffff\0" \
  248. "fdt_high=0xffffffff\0" \
  249. "fdt_addr=0x64f00000\0" \
  250. "kernel_addr=0x65000000\0" \
  251. "scriptaddr=0x80000000\0" \
  252. "scripthdraddr=0x80080000\0" \
  253. "fdtheader_addr_r=0x80100000\0" \
  254. "kernelheader_addr_r=0x80200000\0" \
  255. "kernel_addr_r=0x81000000\0" \
  256. "fdt_addr_r=0x90000000\0" \
  257. "ramdisk_addr_r=0xa0000000\0" \
  258. "load_addr=0xa0000000\0" \
  259. "kernel_size=0x2800000\0" \
  260. "kernel_addr_sd=0x8000\0" \
  261. "kernel_size_sd=0x14000\0" \
  262. BOOTENV \
  263. "boot_scripts=ls1021atwr_boot.scr\0" \
  264. "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
  265. "scan_dev_for_boot_part=" \
  266. "part list ${devtype} ${devnum} devplist; " \
  267. "env exists devplist || setenv devplist 1; " \
  268. "for distro_bootpart in ${devplist}; do " \
  269. "if fstype ${devtype} " \
  270. "${devnum}:${distro_bootpart} " \
  271. "bootfstype; then " \
  272. "run scan_dev_for_boot; " \
  273. "fi; " \
  274. "done\0" \
  275. "scan_dev_for_boot=" \
  276. "echo Scanning ${devtype} " \
  277. "${devnum}:${distro_bootpart}...; " \
  278. "for prefix in ${boot_prefixes}; do " \
  279. "run scan_dev_for_scripts; " \
  280. "done;" \
  281. "\0" \
  282. "boot_a_script=" \
  283. "load ${devtype} ${devnum}:${distro_bootpart} " \
  284. "${scriptaddr} ${prefix}${script}; " \
  285. "env exists secureboot && load ${devtype} " \
  286. "${devnum}:${distro_bootpart} " \
  287. "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
  288. "env exists secureboot " \
  289. "&& esbc_validate ${scripthdraddr};" \
  290. "source ${scriptaddr}\0" \
  291. "installer=load mmc 0:2 $load_addr " \
  292. "/flex_installer_arm32.itb; " \
  293. "bootm $load_addr#ls1021atwr\0" \
  294. "qspi_bootcmd=echo Trying load from qspi..;" \
  295. "sf probe && sf read $load_addr " \
  296. "$kernel_addr $kernel_size && bootm $load_addr#$board\0" \
  297. "nor_bootcmd=echo Trying load from nor..;" \
  298. "cp.b $kernel_addr $load_addr " \
  299. "$kernel_size && bootm $load_addr#$board\0"
  300. #else
  301. #define CONFIG_EXTRA_ENV_SETTINGS \
  302. "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
  303. "initrd_high=0xffffffff\0" \
  304. "fdt_high=0xffffffff\0" \
  305. "fdt_addr=0x64f00000\0" \
  306. "kernel_addr=0x61000000\0" \
  307. "kernelheader_addr=0x60800000\0" \
  308. "scriptaddr=0x80000000\0" \
  309. "scripthdraddr=0x80080000\0" \
  310. "fdtheader_addr_r=0x80100000\0" \
  311. "kernelheader_addr_r=0x80200000\0" \
  312. "kernel_addr_r=0x81000000\0" \
  313. "kernelheader_size=0x40000\0" \
  314. "fdt_addr_r=0x90000000\0" \
  315. "ramdisk_addr_r=0xa0000000\0" \
  316. "load_addr=0xa0000000\0" \
  317. "kernel_size=0x2800000\0" \
  318. "kernel_addr_sd=0x8000\0" \
  319. "kernel_size_sd=0x14000\0" \
  320. "kernelhdr_addr_sd=0x4000\0" \
  321. "kernelhdr_size_sd=0x10\0" \
  322. BOOTENV \
  323. "boot_scripts=ls1021atwr_boot.scr\0" \
  324. "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
  325. "scan_dev_for_boot_part=" \
  326. "part list ${devtype} ${devnum} devplist; " \
  327. "env exists devplist || setenv devplist 1; " \
  328. "for distro_bootpart in ${devplist}; do " \
  329. "if fstype ${devtype} " \
  330. "${devnum}:${distro_bootpart} " \
  331. "bootfstype; then " \
  332. "run scan_dev_for_boot; " \
  333. "fi; " \
  334. "done\0" \
  335. "scan_dev_for_boot=" \
  336. "echo Scanning ${devtype} " \
  337. "${devnum}:${distro_bootpart}...; " \
  338. "for prefix in ${boot_prefixes}; do " \
  339. "run scan_dev_for_scripts; " \
  340. "done;" \
  341. "\0" \
  342. "boot_a_script=" \
  343. "load ${devtype} ${devnum}:${distro_bootpart} " \
  344. "${scriptaddr} ${prefix}${script}; " \
  345. "env exists secureboot && load ${devtype} " \
  346. "${devnum}:${distro_bootpart} " \
  347. "${scripthdraddr} ${prefix}${boot_script_hdr} " \
  348. "&& esbc_validate ${scripthdraddr};" \
  349. "source ${scriptaddr}\0" \
  350. "qspi_bootcmd=echo Trying load from qspi..;" \
  351. "sf probe && sf read $load_addr " \
  352. "$kernel_addr $kernel_size; env exists secureboot " \
  353. "&& sf read $kernelheader_addr_r $kernelheader_addr " \
  354. "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
  355. "bootm $load_addr#$board\0" \
  356. "nor_bootcmd=echo Trying load from nor..;" \
  357. "cp.b $kernel_addr $load_addr " \
  358. "$kernel_size; env exists secureboot " \
  359. "&& cp.b $kernelheader_addr $kernelheader_addr_r " \
  360. "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
  361. "bootm $load_addr#$board\0" \
  362. "sd_bootcmd=echo Trying load from SD ..;" \
  363. "mmcinfo && mmc read $load_addr " \
  364. "$kernel_addr_sd $kernel_size_sd && " \
  365. "env exists secureboot && mmc read $kernelheader_addr_r " \
  366. "$kernelhdr_addr_sd $kernelhdr_size_sd " \
  367. " && esbc_validate ${kernelheader_addr_r};" \
  368. "bootm $load_addr#$board\0"
  369. #endif
  370. #undef CONFIG_BOOTCOMMAND
  371. #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  372. #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
  373. "env exists secureboot && esbc_halt"
  374. #elif defined(CONFIG_SD_BOOT)
  375. #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
  376. "env exists secureboot && esbc_halt;"
  377. #else
  378. #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd;" \
  379. "env exists secureboot && esbc_halt;"
  380. #endif
  381. /*
  382. * Miscellaneous configurable options
  383. */
  384. #define CONFIG_SYS_MEMTEST_START 0x80000000
  385. #define CONFIG_SYS_MEMTEST_END 0x9fffffff
  386. #define CONFIG_SYS_LOAD_ADDR 0x82000000
  387. #define CONFIG_LS102XA_STREAM_ID
  388. #define CONFIG_SYS_INIT_SP_OFFSET \
  389. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  390. #define CONFIG_SYS_INIT_SP_ADDR \
  391. (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  392. #ifdef CONFIG_SPL_BUILD
  393. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  394. #else
  395. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  396. #endif
  397. #define CONFIG_SYS_QE_FW_ADDR 0x60940000
  398. /*
  399. * Environment
  400. */
  401. #define CONFIG_ENV_OVERWRITE
  402. #if defined(CONFIG_SD_BOOT)
  403. #define CONFIG_SYS_MMC_ENV_DEV 0
  404. #endif
  405. #include <asm/fsl_secure_boot.h>
  406. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  407. #endif