ls1021aiot.h 5.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2016 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef __CONFIG_H
  6. #define __CONFIG_H
  7. #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
  8. #define CONFIG_SYS_FSL_CLK
  9. /*
  10. * Size of malloc() pool
  11. */
  12. #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
  13. #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
  14. #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
  15. #define CONFIG_SYS_CLK_FREQ 100000000
  16. #define CONFIG_DDR_CLK_FREQ 100000000
  17. /*
  18. * DDR: 800 MHz ( 1600 MT/s data rate )
  19. */
  20. #define DDR_SDRAM_CFG 0x470c0008
  21. #define DDR_CS0_BNDS 0x008000bf
  22. #define DDR_CS0_CONFIG 0x80014302
  23. #define DDR_TIMING_CFG_0 0x50550004
  24. #define DDR_TIMING_CFG_1 0xbcb38c56
  25. #define DDR_TIMING_CFG_2 0x0040d120
  26. #define DDR_TIMING_CFG_3 0x010e1000
  27. #define DDR_TIMING_CFG_4 0x00000001
  28. #define DDR_TIMING_CFG_5 0x03401400
  29. #define DDR_SDRAM_CFG_2 0x00401010
  30. #define DDR_SDRAM_MODE 0x00061c60
  31. #define DDR_SDRAM_MODE_2 0x00180000
  32. #define DDR_SDRAM_INTERVAL 0x18600618
  33. #define DDR_DDR_WRLVL_CNTL 0x8655f605
  34. #define DDR_DDR_WRLVL_CNTL_2 0x05060607
  35. #define DDR_DDR_WRLVL_CNTL_3 0x05050505
  36. #define DDR_DDR_CDR1 0x80040000
  37. #define DDR_DDR_CDR2 0x00000001
  38. #define DDR_SDRAM_CLK_CNTL 0x02000000
  39. #define DDR_DDR_ZQ_CNTL 0x89080600
  40. #define DDR_CS0_CONFIG_2 0
  41. #define DDR_SDRAM_CFG_MEM_EN 0x80000000
  42. #define SDRAM_CFG2_D_INIT 0x00000010
  43. #define DDR_CDR2_VREF_TRAIN_EN 0x00000080
  44. #define SDRAM_CFG2_FRC_SR 0x80000000
  45. #define SDRAM_CFG_BI 0x00000001
  46. #ifdef CONFIG_RAMBOOT_PBL
  47. #define CONFIG_SYS_FSL_PBL_PBI \
  48. board/freescale/ls1021aiot/ls102xa_pbi.cfg
  49. #endif
  50. #ifdef CONFIG_SD_BOOT
  51. #define CONFIG_SYS_FSL_PBL_RCW \
  52. board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg
  53. #define CONFIG_SPL_LIBCOMMON_SUPPORT
  54. #define CONFIG_SPL_LIBGENERIC_SUPPORT
  55. #define CONFIG_SPL_ENV_SUPPORT
  56. #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  57. #define CONFIG_SPL_I2C_SUPPORT
  58. #define CONFIG_SPL_WATCHDOG_SUPPORT
  59. #define CONFIG_SPL_MMC_SUPPORT
  60. #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
  61. #define CONFIG_SPL_MAX_SIZE 0x1a000
  62. #define CONFIG_SPL_STACK 0x1001d000
  63. #define CONFIG_SPL_PAD_TO 0x1c000
  64. #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
  65. CONFIG_SYS_MONITOR_LEN)
  66. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
  67. #define CONFIG_SPL_BSS_START_ADDR 0x80100000
  68. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
  69. #define CONFIG_SYS_MONITOR_LEN 0x80000
  70. #endif
  71. #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
  72. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  73. #define CONFIG_CHIP_SELECTS_PER_CTRL 4
  74. /*
  75. * Serial Port
  76. */
  77. #define CONFIG_SYS_NS16550_SERIAL
  78. #define CONFIG_SYS_NS16550_REG_SIZE 1
  79. #define CONFIG_SYS_NS16550_CLK get_serial_clock()
  80. /*
  81. * I2C
  82. */
  83. #define CONFIG_CMD_I2C
  84. #define CONFIG_SYS_I2C
  85. #define CONFIG_SYS_I2C_MXC
  86. #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
  87. #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
  88. #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
  89. /* EEPROM */
  90. #define CONFIG_ID_EEPROM
  91. #define CONFIG_SYS_I2C_EEPROM_NXID
  92. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  93. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x51
  94. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  95. /*
  96. * MMC
  97. */
  98. #define CONFIG_CMD_MMC
  99. /* SATA */
  100. #define CONFIG_SCSI_AHCI_PLAT
  101. #ifndef PCI_DEVICE_ID_FREESCALE_AHCI
  102. #define PCI_DEVICE_ID_FREESCALE_AHCI 0x0440
  103. #endif
  104. #define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_FREESCALE, \
  105. PCI_DEVICE_ID_FREESCALE_AHCI}
  106. #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
  107. #define CONFIG_SYS_SCSI_MAX_LUN 1
  108. #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
  109. CONFIG_SYS_SCSI_MAX_LUN)
  110. /* SPI */
  111. #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  112. #define CONFIG_SPI_FLASH_SPANSION
  113. /* QSPI */
  114. #define QSPI0_AMBA_BASE 0x40000000
  115. #define FSL_QSPI_FLASH_SIZE (1 << 24)
  116. #define FSL_QSPI_FLASH_NUM 2
  117. #define CONFIG_SPI_FLASH_SPANSION
  118. #endif
  119. /* DM SPI */
  120. #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
  121. #define CONFIG_CMD_SF
  122. #define CONFIG_DM_SPI_FLASH
  123. #endif
  124. /*
  125. * eTSEC
  126. */
  127. #ifdef CONFIG_TSEC_ENET
  128. #define CONFIG_MII_DEFAULT_TSEC 1
  129. #define CONFIG_TSEC1 1
  130. #define CONFIG_TSEC1_NAME "eTSEC1"
  131. #define CONFIG_TSEC2 1
  132. #define CONFIG_TSEC2_NAME "eTSEC2"
  133. #define TSEC1_PHY_ADDR 1
  134. #define TSEC2_PHY_ADDR 3
  135. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  136. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  137. #define TSEC1_PHYIDX 0
  138. #define TSEC2_PHYIDX 0
  139. #define CONFIG_ETHPRIME "eTSEC2"
  140. #define CONFIG_PHY_ATHEROS
  141. #define CONFIG_HAS_ETH0
  142. #define CONFIG_HAS_ETH1
  143. #define CONFIG_HAS_ETH2
  144. #endif
  145. /* PCIe */
  146. #define CONFIG_PCIE1 /* PCIE controler 1 */
  147. #define CONFIG_PCIE2 /* PCIE controler 2 */
  148. #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
  149. #ifdef CONFIG_PCI
  150. #define CONFIG_PCI_SCAN_SHOW
  151. #endif
  152. #define CONFIG_CMD_MII
  153. #define CONFIG_CMDLINE_TAG
  154. #define CONFIG_PEN_ADDR_BIG_ENDIAN
  155. #define CONFIG_LAYERSCAPE_NS_ACCESS
  156. #define CONFIG_SMP_PEN_ADDR 0x01ee0200
  157. #define COUNTER_FREQUENCY 12500000
  158. #define CONFIG_HWCONFIG
  159. #define HWCONFIG_BUFFER_SIZE 256
  160. #define CONFIG_FSL_DEVICE_DISABLE
  161. #define CONFIG_EXTRA_ENV_SETTINGS \
  162. "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
  163. "initrd_high=0xffffffff\0" \
  164. "fdt_high=0xffffffff\0"
  165. /*
  166. * Miscellaneous configurable options
  167. */
  168. #define CONFIG_CMD_GREPENV
  169. #define CONFIG_CMD_MEMINFO
  170. #define CONFIG_SYS_LOAD_ADDR 0x82000000
  171. #define CONFIG_LS102XA_STREAM_ID
  172. #define CONFIG_SYS_INIT_SP_OFFSET \
  173. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  174. #define CONFIG_SYS_INIT_SP_ADDR \
  175. (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  176. #ifdef CONFIG_SPL_BUILD
  177. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  178. #else
  179. /* start of monitor */
  180. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  181. #endif
  182. #define CONFIG_SYS_QE_FW_ADDR 0x67f40000
  183. /*
  184. * Environment
  185. */
  186. #define CONFIG_ENV_OVERWRITE
  187. #if defined(CONFIG_SD_BOOT)
  188. #define CONFIG_SYS_MMC_ENV_DEV 0
  189. #endif
  190. #define CONFIG_OF_BOARD_SETUP
  191. #define CONFIG_OF_STDOUT_VIA_ALIAS
  192. #include <asm/fsl_secure_boot.h>
  193. #endif