ls1012aqds.h 2.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2016 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef __LS1012AQDS_H__
  6. #define __LS1012AQDS_H__
  7. #include "ls1012a_common.h"
  8. /* DDR */
  9. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  10. #define CONFIG_CHIP_SELECTS_PER_CTRL 1
  11. #define CONFIG_SYS_SDRAM_SIZE 0x40000000
  12. #define CONFIG_CMD_MEMINFO
  13. #define CONFIG_SYS_MEMTEST_START 0x80000000
  14. #define CONFIG_SYS_MEMTEST_END 0x9fffffff
  15. /*
  16. * QIXIS Definitions
  17. */
  18. #define CONFIG_FSL_QIXIS
  19. #ifdef CONFIG_FSL_QIXIS
  20. #define CONFIG_QIXIS_I2C_ACCESS
  21. #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
  22. #define QIXIS_LBMAP_BRDCFG_REG 0x04
  23. #define QIXIS_LBMAP_SWITCH 6
  24. #define QIXIS_LBMAP_MASK 0x08
  25. #define QIXIS_LBMAP_SHIFT 0
  26. #define QIXIS_LBMAP_DFLTBANK 0x00
  27. #define QIXIS_LBMAP_ALTBANK 0x08
  28. #define QIXIS_RST_CTL_RESET 0x31
  29. #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  30. #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  31. #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  32. #endif
  33. /*
  34. * I2C bus multiplexer
  35. */
  36. #define I2C_MUX_PCA_ADDR_PRI 0x77
  37. #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
  38. #define I2C_RETIMER_ADDR 0x18
  39. #define I2C_MUX_CH_DEFAULT 0x8
  40. #define I2C_MUX_CH_CH7301 0xC
  41. #define I2C_MUX_CH5 0xD
  42. #define I2C_MUX_CH7 0xF
  43. #define I2C_MUX_CH_VOL_MONITOR 0xa
  44. /*
  45. * RTC configuration
  46. */
  47. #define RTC
  48. #define CONFIG_RTC_PCF8563 1
  49. #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
  50. /* EEPROM */
  51. #define CONFIG_ID_EEPROM
  52. #define CONFIG_SYS_I2C_EEPROM_NXID
  53. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  54. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  55. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  56. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  57. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  58. /* Voltage monitor on channel 2*/
  59. #define I2C_VOL_MONITOR_ADDR 0x40
  60. #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
  61. #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
  62. #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
  63. /* DSPI */
  64. #define CONFIG_FSL_DSPI1
  65. #define MMAP_DSPI DSPI1_BASE_ADDR
  66. #define CONFIG_SYS_DSPI_CTAR0 1
  67. #define CONFIG_SYS_DSPI_CTAR1 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
  68. DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
  69. DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
  70. DSPI_CTAR_DT(0))
  71. #define CONFIG_SPI_FLASH_SST /* cs1 */
  72. #define CONFIG_SYS_DSPI_CTAR2 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
  73. DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
  74. DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \
  75. DSPI_CTAR_DT(0))
  76. #define CONFIG_SPI_FLASH_STMICRO /* cs2 */
  77. #define CONFIG_SYS_DSPI_CTAR3 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
  78. DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
  79. DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
  80. DSPI_CTAR_DT(0))
  81. #define CONFIG_SPI_FLASH_EON /* cs3 */
  82. /* MMC */
  83. #ifdef CONFIG_MMC
  84. #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
  85. #endif
  86. #define CONFIG_PCIE1 /* PCIE controller 1 */
  87. #define CONFIG_PCI_SCAN_SHOW
  88. #define CONFIG_CMD_MEMINFO
  89. #define CONFIG_SYS_MEMTEST_START 0x80000000
  90. #define CONFIG_SYS_MEMTEST_END 0x9fffffff
  91. #include <asm/fsl_secure_boot.h>
  92. #endif /* __LS1012AQDS_H__ */