km-mpc8360.h 2.4 KB

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  1. /* KMBEC FPGA (PRIO) */
  2. #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
  3. #define CONFIG_SYS_KMBEC_FPGA_SIZE 64
  4. /*
  5. * High Level Configuration Options
  6. */
  7. /*
  8. * QE UEC ethernet configuration
  9. */
  10. #define CONFIG_UEC_ETH1 /* GETH1 */
  11. #define UEC_VERBOSE_DEBUG 1
  12. #define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
  13. #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
  14. #define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
  15. #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
  16. #define CONFIG_SYS_UEC1_PHY_ADDR 0
  17. #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
  18. #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
  19. /*
  20. * System IO Setup
  21. */
  22. #define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI)
  23. /**
  24. * DDR RAM settings
  25. */
  26. #define CONFIG_SYS_DDR_SDRAM_CFG (\
  27. SDRAM_CFG_SDRAM_TYPE_DDR2 | \
  28. SDRAM_CFG_SREN | \
  29. SDRAM_CFG_HSE)
  30. #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
  31. #define CONFIG_SYS_DDR_CLK_CNTL (\
  32. DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  33. #define CONFIG_SYS_DDR_INTERVAL (\
  34. (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
  35. (0x203 << SDRAM_INTERVAL_REFINT_SHIFT))
  36. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
  37. #define CONFIG_SYS_DDRCDR (\
  38. DDRCDR_EN | \
  39. DDRCDR_Q_DRN)
  40. #define CONFIG_SYS_DDR_MODE 0x47860452
  41. #define CONFIG_SYS_DDR_MODE2 0x8080c000
  42. #define CONFIG_SYS_DDR_TIMING_0 (\
  43. (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
  44. (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
  45. (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
  46. (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
  47. (0 << TIMING_CFG0_WWT_SHIFT) | \
  48. (0 << TIMING_CFG0_RRT_SHIFT) | \
  49. (0 << TIMING_CFG0_WRT_SHIFT) | \
  50. (0 << TIMING_CFG0_RWT_SHIFT))
  51. #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
  52. (2 << TIMING_CFG1_WRTORD_SHIFT) | \
  53. (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
  54. (3 << TIMING_CFG1_WRREC_SHIFT) | \
  55. (7 << TIMING_CFG1_REFREC_SHIFT) | \
  56. (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
  57. (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
  58. (3 << TIMING_CFG1_PRETOACT_SHIFT))
  59. #define CONFIG_SYS_DDR_TIMING_2 (\
  60. (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \
  61. (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
  62. (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
  63. (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
  64. (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
  65. (5 << TIMING_CFG2_CPO_SHIFT) | \
  66. (0 << TIMING_CFG2_ADD_LAT_SHIFT))
  67. #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  68. /* EEprom support */
  69. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  70. /*
  71. * PAXE on the local bus CS3
  72. */
  73. #define CONFIG_SYS_PAXE_BASE 0xA0000000
  74. #define CONFIG_SYS_PAXE_SIZE 256