imx8qm_rom7720.h 5.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2017-2018 NXP
  4. */
  5. #ifndef __IMX8QM_ROM7720_H
  6. #define __IMX8QM_ROM7720_H
  7. #include <linux/sizes.h>
  8. #include <asm/arch/imx-regs.h>
  9. #define CONFIG_REMAKE_ELF
  10. #define CONFIG_SPL_MAX_SIZE (124 * 1024)
  11. #define CONFIG_SPL_BSS_START_ADDR 0x00128000
  12. #define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */
  13. #undef CONFIG_BOOTM_NETBSD
  14. #define CONFIG_FSL_USDHC
  15. #define CONFIG_SYS_FSL_ESDHC_ADDR 0
  16. #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
  17. #define CONFIG_ENV_OVERWRITE
  18. #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  19. /* FUSE command */
  20. #define CONFIG_CMD_FUSE
  21. /* Boot M4 */
  22. #define M4_BOOT_ENV \
  23. "m4_0_image=m4_0.bin\0" \
  24. "m4_1_image=m4_1.bin\0" \
  25. "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \
  26. "loadm4image_1=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_1_image}\0" \
  27. "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
  28. "m4boot_1=run loadm4image_1; dcache flush; bootaux ${loadaddr} 1\0" \
  29. #ifdef CONFIG_NAND_BOOT
  30. #define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) "
  31. #else
  32. #define MFG_NAND_PARTITION ""
  33. #endif
  34. #define CONFIG_MFG_ENV_SETTINGS \
  35. "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
  36. "rdinit=/linuxrc " \
  37. "g_mass_storage.stall=0 g_mass_storage.removable=1 " \
  38. "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
  39. "g_mass_storage.iSerialNumber=\"\" "\
  40. MFG_NAND_PARTITION \
  41. "clk_ignore_unused "\
  42. "\0" \
  43. "initrd_addr=0x83800000\0" \
  44. "initrd_high=0xffffffffffffffff\0" \
  45. "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
  46. /* Initial environment variables */
  47. #define CONFIG_EXTRA_ENV_SETTINGS \
  48. CONFIG_MFG_ENV_SETTINGS \
  49. M4_BOOT_ENV \
  50. "script=boot.scr\0" \
  51. "image=Image\0" \
  52. "panel=NULL\0" \
  53. "console=ttyLP0\0" \
  54. "fdt_addr=0x83000000\0" \
  55. "fdt_high=0xffffffffffffffff\0" \
  56. "boot_fdt=try\0" \
  57. "fdt_file=imx8qm-rom7720-a1.dtb\0" \
  58. "initrd_addr=0x83800000\0" \
  59. "initrd_high=0xffffffffffffffff\0" \
  60. "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
  61. "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
  62. "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
  63. "mmcautodetect=yes\0" \
  64. "mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} earlycon\0 " \
  65. "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
  66. "bootscript=echo Running bootscript from mmc ...; " \
  67. "source\0" \
  68. "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
  69. "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
  70. "mmcboot=echo Booting from mmc ...; " \
  71. "run mmcargs; " \
  72. "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
  73. "if run loadfdt; then " \
  74. "booti ${loadaddr} - ${fdt_addr}; " \
  75. "else " \
  76. "echo WARN: Cannot load the DT; " \
  77. "fi; " \
  78. "else " \
  79. "echo wait for boot; " \
  80. "fi;\0" \
  81. "netargs=setenv bootargs console=${console},${baudrate} " \
  82. "root=/dev/nfs " \
  83. "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp rw earlycon\0" \
  84. "netboot=echo Booting from net ...; " \
  85. "run netargs; " \
  86. "if test ${ip_dyn} = yes; then " \
  87. "setenv get_cmd dhcp; " \
  88. "else " \
  89. "setenv get_cmd tftp; " \
  90. "fi; " \
  91. "${get_cmd} ${loadaddr} ${image}; " \
  92. "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
  93. "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
  94. "booti ${loadaddr} - ${fdt_addr}; " \
  95. "else " \
  96. "echo WARN: Cannot load the DT; " \
  97. "fi; " \
  98. "else " \
  99. "booti; " \
  100. "fi;\0"
  101. #define CONFIG_BOOTCOMMAND \
  102. "mmc dev ${mmcdev}; if mmc rescan; then " \
  103. "if run loadbootscript; then " \
  104. "run bootscript; " \
  105. "else " \
  106. "if run loadimage; then " \
  107. "run mmcboot; " \
  108. "else run netboot; " \
  109. "fi; " \
  110. "fi; " \
  111. "else booti ${loadaddr} - ${fdt_addr}; fi"
  112. /* Link Definitions */
  113. #define CONFIG_LOADADDR 0x80280000
  114. #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
  115. #define CONFIG_SYS_INIT_SP_ADDR 0x80200000
  116. /* Default environment is in SD */
  117. #ifdef CONFIG_QSPI_BOOT
  118. #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
  119. #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
  120. #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
  121. #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
  122. #else
  123. #define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
  124. #endif
  125. #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
  126. /* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board,
  127. * USDHC3 is for SD on base board On DDR4 board, USDHC1 is mux for NAND,
  128. * USDHC2 is for SD, USDHC3 is for SD on base board
  129. */
  130. #define CONFIG_SYS_MMC_ENV_DEV 2 /* USDHC3 */
  131. #define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */
  132. #define CONFIG_SYS_FSL_USDHC_NUM 3
  133. /* Size of malloc() pool */
  134. #define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
  135. #define CONFIG_SYS_SDRAM_BASE 0x80000000
  136. #define PHYS_SDRAM_1 0x80000000
  137. #define PHYS_SDRAM_2 0x880000000
  138. #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */
  139. /* LPDDR4 board total DDR is 6GB, DDR4 board total DDR is 4 GB */
  140. #define PHYS_SDRAM_2_SIZE 0x80000000 /* 2 GB */
  141. #define CONFIG_SYS_MEMTEST_START 0xA0000000
  142. #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_1_SIZE >> 2))
  143. /* Serial */
  144. #define CONFIG_BAUDRATE 115200
  145. /* Generic Timer Definitions */
  146. #define COUNTER_FREQUENCY 8000000 /* 8MHz */
  147. /* Networking */
  148. #define CONFIG_FEC_XCV_TYPE RGMII
  149. #define FEC_QUIRK_ENET_MAC
  150. #endif /* __IMX8QM_ROM7720_H */