imx27lite-common.h 4.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2010 Heiko Schocher <hs@denx.de>
  4. *
  5. * based on:
  6. * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
  7. */
  8. #ifndef __IMX27LITE_COMMON_CONFIG_H
  9. #define __IMX27LITE_COMMON_CONFIG_H
  10. /*
  11. * SoC Configuration
  12. */
  13. #define CONFIG_MX27
  14. #define CONFIG_MX27_CLK32 32768 /* OSC32K frequency */
  15. #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
  16. #define CONFIG_SETUP_MEMORY_TAGS 1
  17. #define CONFIG_INITRD_TAG 1
  18. /*
  19. * Lowlevel configuration
  20. */
  21. #define SDRAM_ESDCFG_REGISTER_VAL(cas) \
  22. (ESDCFG_TRC(10) | \
  23. ESDCFG_TRCD(3) | \
  24. ESDCFG_TCAS(cas) | \
  25. ESDCFG_TRRD(1) | \
  26. ESDCFG_TRAS(5) | \
  27. ESDCFG_TWR | \
  28. ESDCFG_TMRD(2) | \
  29. ESDCFG_TRP(2) | \
  30. ESDCFG_TXP(3))
  31. #define SDRAM_ESDCTL_REGISTER_VAL \
  32. (ESDCTL_PRCT(0) | \
  33. ESDCTL_BL | \
  34. ESDCTL_PWDT(0) | \
  35. ESDCTL_SREFR(3) | \
  36. ESDCTL_DSIZ_32 | \
  37. ESDCTL_COL10 | \
  38. ESDCTL_ROW13 | \
  39. ESDCTL_SDE)
  40. #define SDRAM_ALL_VAL 0xf00
  41. #define SDRAM_MODE_REGISTER_VAL 0x33 /* BL: 8, CAS: 3 */
  42. #define SDRAM_EXT_MODE_REGISTER_VAL 0x1000000
  43. #define MPCTL0_VAL 0x1ef15d5
  44. #define SPCTL0_VAL 0x043a1c09
  45. #define CSCR_VAL 0x33f08107
  46. #define PCDR0_VAL 0x120470c3
  47. #define PCDR1_VAL 0x03030303
  48. #define PCCR0_VAL 0xffffffff
  49. #define PCCR1_VAL 0xfffffffc
  50. #define AIPI1_PSR0_VAL 0x20040304
  51. #define AIPI1_PSR1_VAL 0xdffbfcfb
  52. #define AIPI2_PSR0_VAL 0x07ffc200
  53. #define AIPI2_PSR1_VAL 0xffffffff
  54. /*
  55. * Memory Info
  56. */
  57. /* malloc() len */
  58. #define CONFIG_SYS_MALLOC_LEN (0x10000 + 512 * 1024)
  59. /* memtest start address */
  60. #define CONFIG_SYS_MEMTEST_START 0xA0000000
  61. #define CONFIG_SYS_MEMTEST_END 0xA1000000 /* 16MB RAM test */
  62. #define PHYS_SDRAM_1 0xA0000000 /* DDR Start */
  63. #define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
  64. /*
  65. * Serial Driver info
  66. */
  67. #define CONFIG_MXC_UART
  68. #define CONFIG_MXC_UART_BASE UART1_BASE
  69. /*
  70. * Flash & Environment
  71. */
  72. /* Use buffered writes (~10x faster) */
  73. /* Use hardware sector protection */
  74. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
  75. /* CS2 Base address */
  76. #define PHYS_FLASH_1 0xc0000000
  77. /* Flash Base for U-Boot */
  78. #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
  79. #define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE / \
  80. CONFIG_SYS_FLASH_SECT_SZ)
  81. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  82. #define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */
  83. /* Address and size of Redundant Environment Sector */
  84. /*
  85. * Ethernet
  86. */
  87. #define CONFIG_FEC_MXC
  88. #define CONFIG_FEC_MXC_PHYADDR 0x1f
  89. /*
  90. * MTD
  91. */
  92. /*
  93. * NAND
  94. */
  95. #define CONFIG_MXC_NAND_REGS_BASE 0xd8000000
  96. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  97. #define CONFIG_SYS_NAND_BASE 0xd8000000
  98. #define CONFIG_JFFS2_NAND
  99. #define CONFIG_MXC_NAND_HWECC
  100. /*
  101. * U-Boot general configuration
  102. */
  103. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  104. /* Boot Argument Buffer Size */
  105. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  106. #define CONFIG_LOADADDR 0xa0800000 /* loadaddr env var */
  107. #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
  108. #define CONFIG_EXTRA_ENV_SETTINGS \
  109. "netdev=eth0\0" \
  110. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  111. "nfsroot=${serverip}:${rootpath}\0" \
  112. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  113. "addip=setenv bootargs ${bootargs} " \
  114. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  115. ":${hostname}:${netdev}:off panic=1\0" \
  116. "addtty=setenv bootargs ${bootargs}" \
  117. " console=ttymxc0,${baudrate}\0" \
  118. "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
  119. "addmisc=setenv bootargs ${bootargs}\0" \
  120. "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \
  121. "kernel_addr_r=a0800000\0" \
  122. "bootfile=" CONFIG_HOSTNAME "/uImage\0" \
  123. "rootpath=/opt/eldk-4.2-arm/arm\0" \
  124. "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
  125. "run nfsargs addip addtty addmtd addmisc;" \
  126. "bootm\0" \
  127. "bootcmd=run net_nfs\0" \
  128. "load=tftp ${loadaddr} ${u-boot}\0" \
  129. "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
  130. " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
  131. " +${filesize};cp.b ${fileaddr} " \
  132. __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
  133. "upd=run load update\0" \
  134. "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
  135. "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
  136. /* additions for new relocation code, must be added to all boards */
  137. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  138. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
  139. GENERATED_GBL_DATA_SIZE)
  140. #endif /* __IMX27LITE_COMMON_CONFIG_H */