ids8313.h 8.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2013
  4. * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  5. *
  6. * Based on:
  7. * Copyright (c) 2011 IDS GmbH, Germany
  8. * Sergej Stepanov <ste@ids.de>
  9. */
  10. #ifndef __CONFIG_H
  11. #define __CONFIG_H
  12. /*
  13. * High Level Configuration Options
  14. */
  15. #define CONFIG_FSL_ELBC
  16. #define CONFIG_BOOT_RETRY_TIME 900
  17. #define CONFIG_BOOT_RETRY_MIN 30
  18. #define CONFIG_RESET_TO_RETRY
  19. #define CONFIG_SYS_SICRH 0x00000000
  20. #define CONFIG_SYS_SICRL (SICRL_LBC | SICRL_SPI_D)
  21. #define CONFIG_HWCONFIG
  22. /*
  23. * Definitions for initial stack pointer and data area (in DCACHE )
  24. */
  25. #define CONFIG_SYS_INIT_RAM_LOCK
  26. #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
  27. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in DPRAM */
  28. #define CONFIG_SYS_GBL_DATA_SIZE 0x100
  29. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
  30. - CONFIG_SYS_GBL_DATA_SIZE)
  31. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  32. /*
  33. * Internal Definitions
  34. */
  35. /*
  36. * DDR Setup
  37. */
  38. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  39. /*
  40. * Manually set up DDR parameters,
  41. * as this board has not the SPD connected to I2C.
  42. */
  43. #define CONFIG_SYS_DDR_SIZE 256 /* MB */
  44. #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN |\
  45. 0x00010000 |\
  46. CSCONFIG_ROW_BIT_13 |\
  47. CSCONFIG_COL_BIT_10)
  48. #define CONFIG_SYS_DDR_CONFIG_256 (CONFIG_SYS_DDR_CONFIG | \
  49. CSCONFIG_BANK_BIT_3)
  50. #define CONFIG_SYS_DDR_TIMING_3 (1 << 16) /* ext refrec */
  51. #define CONFIG_SYS_DDR_TIMING_0 ((3 << TIMING_CFG0_RWT_SHIFT) |\
  52. (3 << TIMING_CFG0_WRT_SHIFT) |\
  53. (3 << TIMING_CFG0_RRT_SHIFT) |\
  54. (3 << TIMING_CFG0_WWT_SHIFT) |\
  55. (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\
  56. (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\
  57. (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
  58. (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  59. #define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) |\
  60. (12 << TIMING_CFG1_ACTTOPRE_SHIFT) |\
  61. (4 << TIMING_CFG1_ACTTORW_SHIFT) |\
  62. (7 << TIMING_CFG1_CASLAT_SHIFT) |\
  63. (4 << TIMING_CFG1_REFREC_SHIFT) |\
  64. (4 << TIMING_CFG1_WRREC_SHIFT) |\
  65. (2 << TIMING_CFG1_ACTTOACT_SHIFT) |\
  66. (2 << TIMING_CFG1_WRTORD_SHIFT))
  67. #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\
  68. (5 << TIMING_CFG2_CPO_SHIFT) |\
  69. (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\
  70. (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) |\
  71. (0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\
  72. (1 << TIMING_CFG2_CKE_PLS_SHIFT) |\
  73. (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
  74. #define CONFIG_SYS_DDR_INTERVAL ((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\
  75. (0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  76. #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN |\
  77. SDRAM_CFG_2T_EN | SDRAM_CFG_HSE |\
  78. SDRAM_CFG_DBW_32 |\
  79. SDRAM_CFG_SDRAM_TYPE_DDR2)
  80. #define CONFIG_SYS_SDRAM_CFG2 0x00401000
  81. #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) |\
  82. (0x0242 << SDRAM_MODE_SD_SHIFT))
  83. #define CONFIG_SYS_DDR_MODE_2 0x00000000
  84. #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075
  85. #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN |\
  86. DDRCDR_PZ_NOMZ |\
  87. DDRCDR_NZ_NOMZ |\
  88. DDRCDR_ODT |\
  89. DDRCDR_M_ODR |\
  90. DDRCDR_Q_DRN)
  91. /*
  92. * on-board devices
  93. */
  94. #define CONFIG_TSEC1
  95. #define CONFIG_TSEC2
  96. /*
  97. * NOR FLASH setup
  98. */
  99. #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
  100. #define CONFIG_FLASH_SHOW_PROGRESS 50
  101. #define CONFIG_SYS_FLASH_BASE 0xFF800000
  102. #define CONFIG_SYS_FLASH_SIZE 8
  103. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  104. #define CONFIG_SYS_MAX_FLASH_SECT 128
  105. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000
  106. #define CONFIG_SYS_FLASH_WRITE_TOUT 500
  107. /*
  108. * NAND FLASH setup
  109. */
  110. #define CONFIG_SYS_NAND_BASE 0xE1000000
  111. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  112. #define CONFIG_SYS_NAND_MAX_CHIPS 1
  113. #define CONFIG_NAND_FSL_ELBC
  114. #define CONFIG_SYS_NAND_PAGE_SIZE (2048)
  115. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
  116. #define NAND_CACHE_PAGES 64
  117. /*
  118. * MRAM setup
  119. */
  120. #define CONFIG_SYS_MRAM_BASE 0xE2000000
  121. #define CONFIG_SYS_MRAM_SIZE 0x20000 /* 128 Kb */
  122. #define CONFIG_SYS_OR_TIMING_MRAM
  123. /*
  124. * CPLD setup
  125. */
  126. #define CONFIG_SYS_CPLD_BASE 0xE3000000
  127. #define CONFIG_SYS_CPLD_SIZE 0x8000
  128. #define CONFIG_SYS_OR_TIMING_MRAM
  129. /*
  130. * HW-Watchdog
  131. */
  132. #define CONFIG_WATCHDOG 1
  133. #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
  134. /*
  135. * I2C setup
  136. */
  137. #define CONFIG_SYS_I2C
  138. #define CONFIG_SYS_I2C_FSL
  139. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  140. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  141. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
  142. #define CONFIG_RTC_PCF8563
  143. #define CONFIG_SYS_I2C_RTC_ADDR 0x51
  144. /*
  145. * Ethernet setup
  146. */
  147. #ifdef CONFIG_TSEC1
  148. #define CONFIG_HAS_ETH0
  149. #define CONFIG_TSEC1_NAME "TSEC0"
  150. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  151. #define TSEC1_PHY_ADDR 0x1
  152. #define TSEC1_FLAGS TSEC_GIGABIT
  153. #define TSEC1_PHYIDX 0
  154. #endif
  155. #ifdef CONFIG_TSEC2
  156. #define CONFIG_HAS_ETH1
  157. #define CONFIG_TSEC2_NAME "TSEC1"
  158. #define CONFIG_SYS_TSEC2_OFFSET 0x25000
  159. #define TSEC2_PHY_ADDR 0x3
  160. #define TSEC2_FLAGS TSEC_GIGABIT
  161. #define TSEC2_PHYIDX 0
  162. #endif
  163. #define CONFIG_ETHPRIME "TSEC1"
  164. /*
  165. * Serial Port
  166. */
  167. #define CONFIG_SYS_NS16550_SERIAL
  168. #define CONFIG_SYS_NS16550_REG_SIZE 1
  169. #define CONFIG_SYS_BAUDRATE_TABLE \
  170. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  171. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
  172. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
  173. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
  174. #define CONFIG_HAS_FSL_DR_USB
  175. #define CONFIG_SYS_SCCR_USBDRCM 3
  176. /*
  177. * U-Boot environment setup
  178. */
  179. #define CONFIG_BOOTP_BOOTFILESIZE
  180. /*
  181. * The reserved memory
  182. */
  183. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  184. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  185. #define CONFIG_SYS_MALLOC_LEN (8 * 1024 * 1024)
  186. /*
  187. * Environment Configuration
  188. */
  189. #define CONFIG_NETDEV eth1
  190. #define CONFIG_HOSTNAME "ids8313"
  191. #define CONFIG_ROOTPATH "/opt/eldk-4.2/ppc_6xx"
  192. #define CONFIG_BOOTFILE "ids8313/uImage"
  193. #define CONFIG_UBOOTPATH "ids8313/u-boot.bin"
  194. #define CONFIG_FDTFILE "ids8313/ids8313.dtb"
  195. #define CONFIG_LOADADDR 0x400000
  196. #define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo"
  197. /* Initial Memory map for Linux*/
  198. #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
  199. /*
  200. * Miscellaneous configurable options
  201. */
  202. #define CONFIG_SYS_CBSIZE 1024
  203. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  204. #define CONFIG_SYS_MEMTEST_START 0x00001000
  205. #define CONFIG_SYS_MEMTEST_END 0x00C00000
  206. #define CONFIG_SYS_LOAD_ADDR 0x100000
  207. #define CONFIG_LOADS_ECHO
  208. #define CONFIG_TIMESTAMP
  209. #define CONFIG_BOOTCOMMAND "run boot_cramfs"
  210. #undef CONFIG_SYS_LOADS_BAUD_CHANGE
  211. #define CONFIG_JFFS2_NAND
  212. #define CONFIG_JFFS2_DEV "0"
  213. /* mtdparts command line support */
  214. #define CONFIG_EXTRA_ENV_SETTINGS \
  215. "netdev=" __stringify(CONFIG_NETDEV) "\0" \
  216. "ethprime=TSEC1\0" \
  217. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  218. "tftpflash=tftpboot ${loadaddr} ${uboot}; " \
  219. "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
  220. " +${filesize}; " \
  221. "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
  222. " +${filesize}; " \
  223. "cp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \
  224. " ${filesize}; " \
  225. "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
  226. " +${filesize}; " \
  227. "cmp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \
  228. " ${filesize}\0" \
  229. "console=ttyS0\0" \
  230. "fdtaddr=0x780000\0" \
  231. "kernel_addr=ff800000\0" \
  232. "fdtfile=" __stringify(CONFIG_FDTFILE) "\0" \
  233. "setbootargs=setenv bootargs " \
  234. "root=${rootdev} rw console=${console}," \
  235. "${baudrate} ${othbootargs}\0" \
  236. "setipargs=setenv bootargs root=${rootdev} rw " \
  237. "nfsroot=${serverip}:${rootpath} " \
  238. "ip=${ipaddr}:${serverip}:${gatewayip}:" \
  239. "${netmask}:${hostname}:${netdev}:off " \
  240. "console=${console},${baudrate} ${othbootargs}\0" \
  241. "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
  242. "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
  243. "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
  244. "\0"
  245. #define CONFIG_NFSBOOTCOMMAND \
  246. "setenv rootdev /dev/nfs;" \
  247. "run setipargs;run addmtd;" \
  248. "tftp ${loadaddr} ${bootfile};" \
  249. "tftp ${fdtaddr} ${fdtfile};" \
  250. "fdt addr ${fdtaddr};" \
  251. "bootm ${loadaddr} - ${fdtaddr}"
  252. /* UBI Support */
  253. #endif /* __CONFIG_H */