hrcon.h 12 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2014
  4. * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
  5. *
  6. */
  7. #ifndef __CONFIG_H
  8. #define __CONFIG_H
  9. /*
  10. * High Level Configuration Options
  11. */
  12. #define CONFIG_E300 1 /* E300 family */
  13. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
  14. /*
  15. * SERDES
  16. */
  17. #define CONFIG_FSL_SERDES
  18. #define CONFIG_FSL_SERDES1 0xe3000
  19. /*
  20. * DDR Setup
  21. */
  22. #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
  23. #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  24. #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
  25. | DDRCDR_PZ_LOZ \
  26. | DDRCDR_NZ_LOZ \
  27. | DDRCDR_ODT \
  28. | DDRCDR_Q_DRN)
  29. /* 0x7b880001 */
  30. /*
  31. * Manually set up DDR parameters
  32. * consist of one chip NT5TU64M16HG from NANYA
  33. */
  34. #define CONFIG_SYS_DDR_SIZE 128 /* MB */
  35. #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
  36. #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
  37. | CSCONFIG_ODT_RD_NEVER \
  38. | CSCONFIG_ODT_WR_ONLY_CURRENT \
  39. | CSCONFIG_BANK_BIT_3 \
  40. | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
  41. /* 0x80010102 */
  42. #define CONFIG_SYS_DDR_TIMING_3 0
  43. #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  44. | (0 << TIMING_CFG0_WRT_SHIFT) \
  45. | (0 << TIMING_CFG0_RRT_SHIFT) \
  46. | (0 << TIMING_CFG0_WWT_SHIFT) \
  47. | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  48. | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  49. | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  50. | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  51. /* 0x00260802 */
  52. #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
  53. | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  54. | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
  55. | (7 << TIMING_CFG1_CASLAT_SHIFT) \
  56. | (9 << TIMING_CFG1_REFREC_SHIFT) \
  57. | (2 << TIMING_CFG1_WRREC_SHIFT) \
  58. | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  59. | (2 << TIMING_CFG1_WRTORD_SHIFT))
  60. /* 0x26279222 */
  61. #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
  62. | (4 << TIMING_CFG2_CPO_SHIFT) \
  63. | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  64. | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  65. | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  66. | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  67. | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
  68. /* 0x021848c5 */
  69. #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
  70. | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  71. /* 0x08240100 */
  72. #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
  73. | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  74. | SDRAM_CFG_DBW_16)
  75. /* 0x43100000 */
  76. #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
  77. #define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
  78. | (0x0242 << SDRAM_MODE_SD_SHIFT))
  79. /* ODT 150ohm CL=4, AL=0 on SDRAM */
  80. #define CONFIG_SYS_DDR_MODE2 0x00000000
  81. /*
  82. * Memory test
  83. */
  84. #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
  85. #define CONFIG_SYS_MEMTEST_END 0x07f00000
  86. /*
  87. * The reserved memory
  88. */
  89. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  90. #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
  91. #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
  92. /*
  93. * Initial RAM Base Address Setup
  94. */
  95. #define CONFIG_SYS_INIT_RAM_LOCK 1
  96. #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
  97. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
  98. #define CONFIG_SYS_GBL_DATA_OFFSET \
  99. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  100. /*
  101. * FLASH on the Local Bus
  102. */
  103. #if 1
  104. #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  105. #define CONFIG_FLASH_CFI_LEGACY
  106. #define CONFIG_SYS_FLASH_LEGACY_512Kx16
  107. #endif
  108. #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
  109. #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
  110. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  111. #define CONFIG_SYS_MAX_FLASH_SECT 135
  112. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  113. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  114. #define CONFIG_SYS_FPGA_DONE(k) 0x0010
  115. #define CONFIG_SYS_FPGA_COUNT 1
  116. #define CONFIG_SYS_MCLINK_MAX 3
  117. #define CONFIG_SYS_FPGA_PTR \
  118. { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
  119. /*
  120. * Serial Port
  121. */
  122. #define CONFIG_SYS_NS16550_SERIAL
  123. #define CONFIG_SYS_NS16550_REG_SIZE 1
  124. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  125. #define CONFIG_SYS_BAUDRATE_TABLE \
  126. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  127. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
  128. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
  129. /* Pass open firmware flat tree */
  130. /* I2C */
  131. #define CONFIG_SYS_I2C
  132. #define CONFIG_SYS_I2C_FSL
  133. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  134. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  135. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  136. #define CONFIG_PCA953X /* NXP PCA9554 */
  137. #define CONFIG_PCA9698 /* NXP PCA9698 */
  138. #define CONFIG_SYS_I2C_IHS
  139. #define CONFIG_SYS_I2C_IHS_CH0
  140. #define CONFIG_SYS_I2C_IHS_SPEED_0 50000
  141. #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
  142. #define CONFIG_SYS_I2C_IHS_CH1
  143. #define CONFIG_SYS_I2C_IHS_SPEED_1 50000
  144. #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
  145. #define CONFIG_SYS_I2C_IHS_CH2
  146. #define CONFIG_SYS_I2C_IHS_SPEED_2 50000
  147. #define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
  148. #define CONFIG_SYS_I2C_IHS_CH3
  149. #define CONFIG_SYS_I2C_IHS_SPEED_3 50000
  150. #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
  151. #ifdef CONFIG_HRCON_DH
  152. #define CONFIG_SYS_I2C_IHS_DUAL
  153. #define CONFIG_SYS_I2C_IHS_CH0_1
  154. #define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000
  155. #define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F
  156. #define CONFIG_SYS_I2C_IHS_CH1_1
  157. #define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000
  158. #define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F
  159. #define CONFIG_SYS_I2C_IHS_CH2_1
  160. #define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000
  161. #define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F
  162. #define CONFIG_SYS_I2C_IHS_CH3_1
  163. #define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000
  164. #define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F
  165. #endif
  166. /*
  167. * Software (bit-bang) I2C driver configuration
  168. */
  169. #define CONFIG_SYS_I2C_SOFT
  170. #define CONFIG_SYS_I2C_SOFT_SPEED 50000
  171. #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
  172. #define I2C_SOFT_DECLARATIONS2
  173. #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
  174. #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
  175. #define I2C_SOFT_DECLARATIONS3
  176. #define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
  177. #define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
  178. #define I2C_SOFT_DECLARATIONS4
  179. #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
  180. #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
  181. #define I2C_SOFT_DECLARATIONS5
  182. #define CONFIG_SYS_I2C_SOFT_SPEED_5 50000
  183. #define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F
  184. #define I2C_SOFT_DECLARATIONS6
  185. #define CONFIG_SYS_I2C_SOFT_SPEED_6 50000
  186. #define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F
  187. #define I2C_SOFT_DECLARATIONS7
  188. #define CONFIG_SYS_I2C_SOFT_SPEED_7 50000
  189. #define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F
  190. #define I2C_SOFT_DECLARATIONS8
  191. #define CONFIG_SYS_I2C_SOFT_SPEED_8 50000
  192. #define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F
  193. #ifdef CONFIG_HRCON_DH
  194. #define I2C_SOFT_DECLARATIONS9
  195. #define CONFIG_SYS_I2C_SOFT_SPEED_9 50000
  196. #define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F
  197. #define I2C_SOFT_DECLARATIONS10
  198. #define CONFIG_SYS_I2C_SOFT_SPEED_10 50000
  199. #define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F
  200. #define I2C_SOFT_DECLARATIONS11
  201. #define CONFIG_SYS_I2C_SOFT_SPEED_11 50000
  202. #define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F
  203. #define I2C_SOFT_DECLARATIONS12
  204. #define CONFIG_SYS_I2C_SOFT_SPEED_12 50000
  205. #define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F
  206. #endif
  207. #ifdef CONFIG_HRCON_DH
  208. #define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20}
  209. #define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8}
  210. #define CONFIG_HRCON_FANS { {10, 0x4c}, {11, 0x4c}, \
  211. {12, 0x4c} }
  212. #else
  213. #define CONFIG_SYS_ICS8N3QV01_I2C {9, 10, 11, 12}
  214. #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
  215. #define CONFIG_HRCON_FANS { {6, 0x4c}, {7, 0x4c}, \
  216. {8, 0x4c} }
  217. #endif
  218. #ifndef __ASSEMBLY__
  219. void fpga_gpio_set(unsigned int bus, int pin);
  220. void fpga_gpio_clear(unsigned int bus, int pin);
  221. int fpga_gpio_get(unsigned int bus, int pin);
  222. void fpga_control_set(unsigned int bus, int pin);
  223. void fpga_control_clear(unsigned int bus, int pin);
  224. #endif
  225. #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
  226. #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
  227. #define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4)
  228. #ifdef CONFIG_HRCON_DH
  229. #define I2C_ACTIVE \
  230. do { \
  231. if (I2C_ADAP_HWNR > 7) \
  232. fpga_control_set(I2C_FPGA_IDX, 0x0004); \
  233. else \
  234. fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
  235. } while (0)
  236. #else
  237. #define I2C_ACTIVE { }
  238. #endif
  239. #define I2C_TRISTATE { }
  240. #define I2C_READ \
  241. (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
  242. #define I2C_SDA(bit) \
  243. do { \
  244. if (bit) \
  245. fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
  246. else \
  247. fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
  248. } while (0)
  249. #define I2C_SCL(bit) \
  250. do { \
  251. if (bit) \
  252. fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
  253. else \
  254. fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
  255. } while (0)
  256. #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
  257. /*
  258. * Software (bit-bang) MII driver configuration
  259. */
  260. #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
  261. #define CONFIG_BITBANGMII_MULTI
  262. /*
  263. * OSD Setup
  264. */
  265. #define CONFIG_SYS_OSD_SCREENS 1
  266. #define CONFIG_SYS_DP501_DIFFERENTIAL
  267. #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
  268. #ifdef CONFIG_HRCON_DH
  269. #define CONFIG_SYS_OSD_DH
  270. #endif
  271. /*
  272. * General PCI
  273. * Addresses are mapped 1-1.
  274. */
  275. #define CONFIG_SYS_PCIE1_BASE 0xA0000000
  276. #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
  277. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
  278. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
  279. #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
  280. #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
  281. #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
  282. #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
  283. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
  284. /* enable PCIE clock */
  285. #define CONFIG_SYS_SCCR_PCIEXP1CM 1
  286. #define CONFIG_PCI_INDIRECT_BRIDGE
  287. #define CONFIG_PCIE
  288. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
  289. #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
  290. /*
  291. * TSEC
  292. */
  293. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  294. #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
  295. /*
  296. * TSEC ethernet configuration
  297. */
  298. #define CONFIG_TSEC1
  299. #define CONFIG_TSEC1_NAME "eTSEC0"
  300. #define TSEC1_PHY_ADDR 1
  301. #define TSEC1_PHYIDX 0
  302. #define TSEC1_FLAGS TSEC_GIGABIT
  303. /* Options are: eTSEC[0-1] */
  304. #define CONFIG_ETHPRIME "eTSEC0"
  305. /*
  306. * Environment
  307. */
  308. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  309. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  310. /*
  311. * Command line configuration.
  312. */
  313. /*
  314. * Miscellaneous configurable options
  315. */
  316. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  317. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
  318. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  319. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  320. /*
  321. * For booting Linux, the board info and command line data
  322. * have to be in the first 256 MB of memory, since this is
  323. * the maximum mapped by the Linux kernel during initialization.
  324. */
  325. #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
  326. /*
  327. * Environment Configuration
  328. */
  329. #define CONFIG_ENV_OVERWRITE
  330. #if defined(CONFIG_TSEC_ENET)
  331. #define CONFIG_HAS_ETH0
  332. #endif
  333. #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
  334. #define CONFIG_HOSTNAME "hrcon"
  335. #define CONFIG_ROOTPATH "/opt/nfsroot"
  336. #define CONFIG_BOOTFILE "uImage"
  337. #define CONFIG_EXTRA_ENV_SETTINGS \
  338. "netdev=eth0\0" \
  339. "consoledev=ttyS1\0" \
  340. "u-boot=u-boot.bin\0" \
  341. "kernel_addr=1000000\0" \
  342. "fdt_addr=C00000\0" \
  343. "fdtfile=hrcon.dtb\0" \
  344. "load=tftp ${loadaddr} ${u-boot}\0" \
  345. "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
  346. " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
  347. " +${filesize};cp.b ${fileaddr} " \
  348. __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
  349. "upd=run load update\0" \
  350. #define CONFIG_NFSBOOTCOMMAND \
  351. "setenv bootargs root=/dev/nfs rw " \
  352. "nfsroot=$serverip:$rootpath " \
  353. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  354. "console=$consoledev,$baudrate $othbootargs;" \
  355. "tftp ${kernel_addr} $bootfile;" \
  356. "tftp ${fdt_addr} $fdtfile;" \
  357. "bootm ${kernel_addr} - ${fdt_addr}"
  358. #define CONFIG_MMCBOOTCOMMAND \
  359. "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
  360. "console=$consoledev,$baudrate $othbootargs;" \
  361. "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \
  362. "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \
  363. "bootm ${kernel_addr} - ${fdt_addr}"
  364. #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
  365. #endif /* __CONFIG_H */