highbank.h 1.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2010-2011 Calxeda, Inc.
  4. */
  5. #ifndef __CONFIG_H
  6. #define __CONFIG_H
  7. #define CONFIG_SYS_BOOTMAPSZ (16 << 20)
  8. #define CONFIG_SYS_TIMER_RATE (150000000/256)
  9. #define CONFIG_SYS_TIMER_COUNTER (0xFFF34000 + 0x4)
  10. #define CONFIG_SYS_TIMER_COUNTS_DOWN
  11. /*
  12. * Size of malloc() pool
  13. */
  14. #define CONFIG_SYS_MALLOC_LEN (512 * 1024)
  15. #define CONFIG_PL011_CLOCK 150000000
  16. #define CONFIG_PL01x_PORTS { (void *)(0xFFF36000) }
  17. #define CONFIG_SYS_BOOTCOUNT_LE /* Use little-endian accessors */
  18. #define CONFIG_SCSI_AHCI_PLAT
  19. #define CONFIG_SYS_SCSI_MAX_SCSI_ID 5
  20. #define CONFIG_SYS_SCSI_MAX_LUN 1
  21. #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
  22. CONFIG_SYS_SCSI_MAX_LUN)
  23. #define CONFIG_CALXEDA_XGMAC
  24. /*
  25. * Command line configuration.
  26. */
  27. #define CONFIG_BOOT_RETRY_TIME -1
  28. #define CONFIG_RESET_TO_RETRY
  29. /*
  30. * Miscellaneous configurable options
  31. */
  32. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  33. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  34. #define CONFIG_SYS_LOAD_ADDR 0x800000
  35. #define CONFIG_SYS_64BIT_LBA
  36. /*-----------------------------------------------------------------------
  37. * Physical Memory Map
  38. * The DRAM is already setup, so do not touch the DT node later.
  39. */
  40. #define PHYS_SDRAM_1_SIZE (4089 << 20)
  41. #define CONFIG_SYS_MEMTEST_START 0x100000
  42. #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1_SIZE - 0x100000)
  43. /* Environment data setup
  44. */
  45. #define CONFIG_SYS_NVRAM_BASE_ADDR 0xfff88000 /* NVRAM base address */
  46. #define CONFIG_SYS_NVRAM_SIZE 0x8000 /* NVRAM size */
  47. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  48. #define CONFIG_SYS_INIT_SP_ADDR 0x01000000
  49. #define CONFIG_SKIP_LOWLEVEL_INIT
  50. #endif