gardena-smart-gateway-at91sam.h 2.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2012 Atmel Corporation
  4. * Copyright (C) 2019 Stefan Roese <sr@denx.de>
  5. *
  6. * Configuation settings for the GARDENA smart Gateway (AT91SAM9G25)
  7. */
  8. #ifndef __CONFIG_H__
  9. #define __CONFIG_H__
  10. /* ARM asynchronous clock */
  11. #define CONFIG_SYS_AT91_SLOW_CLOCK 32768
  12. #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
  13. #ifndef CONFIG_SPL_BUILD
  14. #define CONFIG_SKIP_LOWLEVEL_INIT
  15. #endif
  16. #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
  17. /* general purpose I/O */
  18. #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
  19. /* SDRAM */
  20. #define CONFIG_SYS_SDRAM_BASE 0x20000000
  21. #define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */
  22. #define CONFIG_SYS_INIT_SP_ADDR \
  23. (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
  24. #define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024)
  25. /* NAND flash */
  26. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  27. #define CONFIG_SYS_NAND_BASE 0x40000000
  28. #define CONFIG_SYS_NAND_DBW_8 1
  29. /* our ALE is AD21 */
  30. #define CONFIG_SYS_NAND_MASK_ALE BIT(21)
  31. /* our CLE is AD22 */
  32. #define CONFIG_SYS_NAND_MASK_CLE BIT(22)
  33. #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
  34. #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
  35. #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
  36. /* SPL */
  37. #define CONFIG_SPL_MAX_SIZE 0x7000
  38. #define CONFIG_SPL_STACK 0x308000
  39. #define CONFIG_SPL_BSS_START_ADDR 0x20000000
  40. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
  41. #define CONFIG_SYS_SPL_MALLOC_START 0x20080000
  42. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
  43. #define CONFIG_SYS_MONITOR_LEN (512 << 10)
  44. #define CONFIG_SYS_MASTER_CLOCK 132096000
  45. #define CONFIG_SYS_AT91_PLLA 0x20c73f03
  46. #define CONFIG_SYS_MCKR 0x1301
  47. #define CONFIG_SYS_MCKR_CSS 0x1302
  48. #define CONFIG_SPL_NAND_DRIVERS
  49. #define CONFIG_SPL_NAND_BASE
  50. #define CONFIG_SPL_NAND_RAW_ONLY
  51. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
  52. #define CONFIG_SYS_NAND_U_BOOT_SIZE 0xa0000
  53. #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
  54. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
  55. #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
  56. #define CONFIG_SYS_NAND_5_ADDR_CYCLE
  57. #define CONFIG_SYS_NAND_PAGE_SIZE 0x800
  58. #define CONFIG_SYS_NAND_PAGE_COUNT 64
  59. #define CONFIG_SYS_NAND_OOBSIZE 64
  60. #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
  61. #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
  62. #define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS
  63. #define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
  64. #endif