exynos5-common.h 4.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2013 Samsung Electronics
  4. *
  5. * Configuration settings for the SAMSUNG EXYNOS5 board.
  6. */
  7. #ifndef __CONFIG_EXYNOS5_COMMON_H
  8. #define __CONFIG_EXYNOS5_COMMON_H
  9. #define CONFIG_EXYNOS5 /* Exynos5 Family */
  10. #include "exynos-common.h"
  11. #define CONFIG_EXYNOS_SPL
  12. #ifdef FTRACE
  13. #define CONFIG_TRACE
  14. #define CONFIG_TRACE_BUFFER_SIZE (16 << 20)
  15. #define CONFIG_TRACE_EARLY_SIZE (8 << 20)
  16. #define CONFIG_TRACE_EARLY
  17. #define CONFIG_TRACE_EARLY_ADDR 0x50000000
  18. #endif
  19. /* Enable ACE acceleration for SHA1 and SHA256 */
  20. #define CONFIG_EXYNOS_ACE_SHA
  21. /* Power Down Modes */
  22. #define S5P_CHECK_SLEEP 0x00000BAD
  23. #define S5P_CHECK_DIDLE 0xBAD00000
  24. #define S5P_CHECK_LPA 0xABAD0000
  25. /* Offset for inform registers */
  26. #define INFORM0_OFFSET 0x800
  27. #define INFORM1_OFFSET 0x804
  28. #define INFORM2_OFFSET 0x808
  29. #define INFORM3_OFFSET 0x80c
  30. /* select serial console configuration */
  31. #define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
  32. /* Thermal Management Unit */
  33. #define CONFIG_EXYNOS_TMU
  34. /* MMC SPL */
  35. #define COPY_BL2_FNPTR_ADDR 0x02020030
  36. /* specific .lds file */
  37. /* Boot Argument Buffer Size */
  38. /* memtest works on */
  39. #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
  40. #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
  41. #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
  42. #define CONFIG_RD_LVL
  43. #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
  44. #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
  45. #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
  46. #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
  47. #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
  48. #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
  49. #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
  50. #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
  51. #define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
  52. #define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
  53. #define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
  54. #define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
  55. #define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
  56. #define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
  57. #define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
  58. #define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
  59. #define CONFIG_SYS_MONITOR_BASE 0x00000000
  60. #define CONFIG_SYS_MMC_ENV_DEV 0
  61. #define CONFIG_SECURE_BL1_ONLY
  62. /* Secure FW size configuration */
  63. #ifdef CONFIG_SECURE_BL1_ONLY
  64. #define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
  65. #else
  66. #define CONFIG_SEC_FW_SIZE 0
  67. #endif
  68. /* Configuration of BL1, BL2, ENV Blocks on mmc */
  69. #define CONFIG_RES_BLOCK_SIZE (512)
  70. #define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
  71. #define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */
  72. #define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
  73. #define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
  74. /* U-Boot copy size from boot Media to DRAM.*/
  75. #define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512)
  76. #define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)
  77. #define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058
  78. #define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
  79. /* I2C */
  80. #define CONFIG_SYS_I2C_S3C24X0
  81. #define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */
  82. #define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0
  83. /* SPI */
  84. /* Ethernet Controllor Driver */
  85. #ifdef CONFIG_CMD_NET
  86. #define CONFIG_ENV_SROM_BANK 1
  87. #endif /*CONFIG_CMD_NET*/
  88. /* Enable Time Command */
  89. /* USB */
  90. /* USB boot mode */
  91. #define CONFIG_USB_BOOTING
  92. #define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070
  93. #define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002
  94. #define EXYNOS_IRAM_SECONDARY_BASE 0x02020018
  95. #define BOOT_TARGET_DEVICES(func) \
  96. func(MMC, mmc, 2) \
  97. func(MMC, mmc, 1) \
  98. func(MMC, mmc, 0) \
  99. func(PXE, pxe, na) \
  100. func(DHCP, dhcp, na)
  101. #include <config_distro_bootcmd.h>
  102. #ifndef MEM_LAYOUT_ENV_SETTINGS
  103. /* 2GB RAM, bootm size of 256M, load scripts after that */
  104. #define MEM_LAYOUT_ENV_SETTINGS \
  105. "bootm_size=0x10000000\0" \
  106. "kernel_addr_r=0x42000000\0" \
  107. "fdt_addr_r=0x43000000\0" \
  108. "ramdisk_addr_r=0x43300000\0" \
  109. "scriptaddr=0x50000000\0" \
  110. "pxefile_addr_r=0x51000000\0"
  111. #endif
  112. #ifndef EXYNOS_DEVICE_SETTINGS
  113. #define EXYNOS_DEVICE_SETTINGS \
  114. "stdin=serial\0" \
  115. "stdout=serial\0" \
  116. "stderr=serial\0"
  117. #endif
  118. #ifndef EXYNOS_FDTFILE_SETTING
  119. #define EXYNOS_FDTFILE_SETTING
  120. #endif
  121. #define CONFIG_EXTRA_ENV_SETTINGS \
  122. EXYNOS_DEVICE_SETTINGS \
  123. EXYNOS_FDTFILE_SETTING \
  124. MEM_LAYOUT_ENV_SETTINGS \
  125. BOOTENV
  126. #endif /* __CONFIG_EXYNOS5_COMMON_H */