eb_cpu5282.h 7.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Configuation settings for the BuS EB+CPU5283 boards (aka EB+MCF-EV123)
  4. *
  5. * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
  6. */
  7. #ifndef _CONFIG_EB_CPU5282_H_
  8. #define _CONFIG_EB_CPU5282_H_
  9. #undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP
  10. /*----------------------------------------------------------------------*
  11. * High Level Configuration Options (easy to change) *
  12. *----------------------------------------------------------------------*/
  13. #define CONFIG_MCFUART
  14. #define CONFIG_SYS_UART_PORT (0)
  15. #undef CONFIG_MONITOR_IS_IN_RAM /* starts uboot direct */
  16. #define CONFIG_BOOTCOMMAND "printenv"
  17. /*----------------------------------------------------------------------*
  18. * Options *
  19. *----------------------------------------------------------------------*/
  20. #define CONFIG_BOOT_RETRY_TIME -1
  21. #define CONFIG_RESET_TO_RETRY
  22. #define CONFIG_SPLASH_SCREEN
  23. #define CONFIG_HW_WATCHDOG
  24. #define STATUS_LED_ACTIVE 0
  25. /*----------------------------------------------------------------------*
  26. * Configuration for environment *
  27. * Environment is in the second sector of the first 256k of flash *
  28. *----------------------------------------------------------------------*/
  29. /*
  30. * BOOTP options
  31. */
  32. #define CONFIG_BOOTP_BOOTFILESIZE
  33. /*
  34. * Command line configuration.
  35. */
  36. #define CONFIG_MCFTMR
  37. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  38. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  39. #define CONFIG_SYS_LOAD_ADDR 0x20000
  40. #define CONFIG_SYS_MEMTEST_START 0x100000
  41. #define CONFIG_SYS_MEMTEST_END 0x400000
  42. /*#define CONFIG_SYS_DRAM_TEST 1 */
  43. #undef CONFIG_SYS_DRAM_TEST
  44. /*----------------------------------------------------------------------*
  45. * Clock and PLL Configuration *
  46. *----------------------------------------------------------------------*/
  47. #define CONFIG_SYS_CLK 80000000 /* 8MHz * 8 */
  48. /* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */
  49. #define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */
  50. #define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
  51. /*----------------------------------------------------------------------*
  52. * Network *
  53. *----------------------------------------------------------------------*/
  54. #define CONFIG_MCFFEC
  55. #define CONFIG_MII_INIT 1
  56. #define CONFIG_SYS_DISCOVER_PHY
  57. #define CONFIG_SYS_RX_ETH_BUFFER 8
  58. #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  59. #define CONFIG_SYS_FEC0_PINMUX 0
  60. #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
  61. #define MCFFEC_TOUT_LOOP 50000
  62. #define CONFIG_OVERWRITE_ETHADDR_ONCE
  63. /*-------------------------------------------------------------------------
  64. * Low Level Configuration Settings
  65. * (address mappings, register initial values, etc.)
  66. * You should know what you are doing if you make changes here.
  67. *-----------------------------------------------------------------------*/
  68. #define CONFIG_SYS_MBAR 0x40000000
  69. /*-----------------------------------------------------------------------
  70. * Definitions for initial stack pointer and data area (in DPRAM)
  71. *-----------------------------------------------------------------------*/
  72. #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
  73. #define CONFIG_SYS_INIT_RAM_SIZE 0x10000
  74. #define CONFIG_SYS_GBL_DATA_OFFSET \
  75. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  76. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  77. /*-----------------------------------------------------------------------
  78. * Start addresses for the final memory configuration
  79. * (Set up by the startup code)
  80. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  81. */
  82. #define CONFIG_SYS_SDRAM_BASE0 0x00000000
  83. #define CONFIG_SYS_SDRAM_SIZE0 16 /* SDRAM size in MB */
  84. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE0
  85. #define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE0
  86. #define CONFIG_SYS_MONITOR_LEN 0x20000
  87. #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
  88. #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
  89. /*
  90. * For booting Linux, the board info and command line data
  91. * have to be in the first 8 MB of memory, since this is
  92. * the maximum mapped by the Linux kernel during initialization ??
  93. */
  94. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  95. /*-----------------------------------------------------------------------
  96. * FLASH organization
  97. */
  98. #define CONFIG_FLASH_SHOW_PROGRESS 45
  99. #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
  100. #define CONFIG_SYS_INT_FLASH_BASE 0xF0000000
  101. #define CONFIG_SYS_INT_FLASH_ENABLE 0x21
  102. #define CONFIG_SYS_MAX_FLASH_SECT 128
  103. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  104. #define CONFIG_SYS_FLASH_ERASE_TOUT 10000000
  105. #define CONFIG_SYS_FLASH_SIZE 16*1024*1024
  106. #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  107. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
  108. /*-----------------------------------------------------------------------
  109. * Cache Configuration
  110. */
  111. #define CONFIG_SYS_CACHELINE_SIZE 16
  112. #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  113. CONFIG_SYS_INIT_RAM_SIZE - 8)
  114. #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  115. CONFIG_SYS_INIT_RAM_SIZE - 4)
  116. #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
  117. #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
  118. CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
  119. CF_ACR_EN | CF_ACR_SM_ALL)
  120. #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
  121. CF_CACR_CEIB | CF_CACR_DBWE | \
  122. CF_CACR_EUSP)
  123. /*-----------------------------------------------------------------------
  124. * Memory bank definitions
  125. */
  126. #define CONFIG_SYS_CS0_BASE 0xFF000000
  127. #define CONFIG_SYS_CS0_CTRL 0x00001980
  128. #define CONFIG_SYS_CS0_MASK 0x00FF0001
  129. #define CONFIG_SYS_CS2_BASE 0xE0000000
  130. #define CONFIG_SYS_CS2_CTRL 0x00001980
  131. #define CONFIG_SYS_CS2_MASK 0x000F0001
  132. #define CONFIG_SYS_CS3_BASE 0xE0100000
  133. #define CONFIG_SYS_CS3_CTRL 0x00001980
  134. #define CONFIG_SYS_CS3_MASK 0x000F0001
  135. /*-----------------------------------------------------------------------
  136. * Port configuration
  137. */
  138. #define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */
  139. #define CONFIG_SYS_PADDR 0x0000000
  140. #define CONFIG_SYS_PADAT 0x0000000
  141. #define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */
  142. #define CONFIG_SYS_PBDDR 0x0000000
  143. #define CONFIG_SYS_PBDAT 0x0000000
  144. #define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */
  145. #define CONFIG_SYS_PCDDR 0x0000000
  146. #define CONFIG_SYS_PCDAT 0x0000000
  147. #define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */
  148. #define CONFIG_SYS_PCDDR 0x0000000
  149. #define CONFIG_SYS_PCDAT 0x0000000
  150. #define CONFIG_SYS_PASPAR 0x0F0F
  151. #define CONFIG_SYS_PEHLPAR 0xC0
  152. #define CONFIG_SYS_PUAPAR 0x0F
  153. #define CONFIG_SYS_DDRUA 0x05
  154. #define CONFIG_SYS_PJPAR 0xFF
  155. /*-----------------------------------------------------------------------
  156. * I2C
  157. */
  158. #define CONFIG_SYS_I2C
  159. #define CONFIG_SYS_I2C_FSL
  160. #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
  161. #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
  162. #define CONFIG_SYS_FSL_I2C_SPEED 100000
  163. #define CONFIG_SYS_FSL_I2C_SLAVE 0
  164. #ifdef CONFIG_CMD_DATE
  165. #define CONFIG_RTC_DS1338
  166. #define CONFIG_I2C_RTC_ADDR 0x68
  167. #endif
  168. /*-----------------------------------------------------------------------
  169. * VIDEO configuration
  170. */
  171. #ifdef CONFIG_VIDEO
  172. #define CONFIG_VIDEO_VCXK 1
  173. #define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 2
  174. #define CONFIG_SYS_VCXK_DOUBLEBUFFERED 1
  175. #define CONFIG_SYS_VCXK_BASE CONFIG_SYS_CS2_BASE
  176. #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT MCFGPTB_GPTPORT
  177. #define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR
  178. #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN 0x0001
  179. #define CONFIG_SYS_VCXK_ENABLE_PORT MCFGPTB_GPTPORT
  180. #define CONFIG_SYS_VCXK_ENABLE_DDR MCFGPTB_GPTDDR
  181. #define CONFIG_SYS_VCXK_ENABLE_PIN 0x0002
  182. #define CONFIG_SYS_VCXK_REQUEST_PORT MCFGPTB_GPTPORT
  183. #define CONFIG_SYS_VCXK_REQUEST_DDR MCFGPTB_GPTDDR
  184. #define CONFIG_SYS_VCXK_REQUEST_PIN 0x0004
  185. #define CONFIG_SYS_VCXK_INVERT_PORT MCFGPIO_PORTE
  186. #define CONFIG_SYS_VCXK_INVERT_DDR MCFGPIO_DDRE
  187. #define CONFIG_SYS_VCXK_INVERT_PIN MCFGPIO_PORT2
  188. #endif /* CONFIG_VIDEO */
  189. #endif /* _CONFIG_M5282EVB_H */
  190. /*---------------------------------------------------------------------*/