dra7xx_evm.h 3.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2013
  4. * Texas Instruments Incorporated.
  5. * Lokesh Vutla <lokeshvutla@ti.com>
  6. *
  7. * Configuration settings for the TI DRA7XX board.
  8. * See ti_omap5_common.h for omap5 common settings.
  9. */
  10. #ifndef __CONFIG_DRA7XX_EVM_H
  11. #define __CONFIG_DRA7XX_EVM_H
  12. #include <environment/ti/dfu.h>
  13. #define CONFIG_IODELAY_RECALIBRATION
  14. #define CONFIG_VERY_BIG_RAM
  15. #define CONFIG_MAX_MEM_MAPPED 0x80000000
  16. #ifndef CONFIG_QSPI_BOOT
  17. /* MMC ENV related defines */
  18. #define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
  19. #endif
  20. #if (CONFIG_CONS_INDEX == 1)
  21. #define CONSOLEDEV "ttyS0"
  22. #elif (CONFIG_CONS_INDEX == 3)
  23. #define CONSOLEDEV "ttyS2"
  24. #endif
  25. #define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */
  26. #define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */
  27. #define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */
  28. #define CONFIG_ENV_EEPROM_IS_ON_I2C
  29. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
  30. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  31. #define CONFIG_SYS_OMAP_ABE_SYSCK
  32. #ifndef CONFIG_SPL_BUILD
  33. #define DFUARGS \
  34. "dfu_bufsiz=0x10000\0" \
  35. DFU_ALT_INFO_MMC \
  36. DFU_ALT_INFO_EMMC \
  37. DFU_ALT_INFO_RAM \
  38. DFU_ALT_INFO_QSPI
  39. #endif
  40. #ifdef CONFIG_SPL_BUILD
  41. #undef CONFIG_CMD_BOOTD
  42. #ifdef CONFIG_SPL_DFU
  43. #define CONFIG_SPL_LOAD_FIT_ADDRESS 0x80200000
  44. #define DFUARGS \
  45. "dfu_bufsiz=0x10000\0" \
  46. DFU_ALT_INFO_RAM
  47. #endif
  48. #endif
  49. #include <configs/ti_omap5_common.h>
  50. /* Enhance our eMMC support / experience. */
  51. #define CONFIG_HSMMC2_8BIT
  52. /* CPSW Ethernet */
  53. #define CONFIG_BOOTP_SEND_HOSTNAME
  54. #define CONFIG_NET_RETRY_COUNT 10
  55. /*
  56. * Default to using SPI for environment, etc.
  57. * 0x000000 - 0x040000 : QSPI.SPL (256KiB)
  58. * 0x040000 - 0x140000 : QSPI.u-boot (1MiB)
  59. * 0x140000 - 0x1C0000 : QSPI.u-boot-spl-os (512KiB)
  60. * 0x1C0000 - 0x1D0000 : QSPI.u-boot-env (64KiB)
  61. * 0x1D0000 - 0x1E0000 : QSPI.u-boot-env.backup1 (64KiB)
  62. * 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB)
  63. * 0x9E0000 - 0x2000000 : USERLAND
  64. */
  65. #define CONFIG_SYS_SPI_KERNEL_OFFS 0x1E0000
  66. #define CONFIG_SYS_SPI_ARGS_OFFS 0x140000
  67. #define CONFIG_SYS_SPI_ARGS_SIZE 0x80000
  68. /* SPI SPL */
  69. /* USB xHCI HOST */
  70. #define CONFIG_USB_XHCI_OMAP
  71. #define CONFIG_OMAP_USB2PHY2_HOST
  72. /* SATA */
  73. #define CONFIG_SCSI_AHCI_PLAT
  74. /* NAND support */
  75. #ifdef CONFIG_MTD_RAW_NAND
  76. /* NAND: device related configs */
  77. #define CONFIG_SYS_NAND_PAGE_SIZE 2048
  78. #define CONFIG_SYS_NAND_OOBSIZE 64
  79. #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
  80. #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
  81. CONFIG_SYS_NAND_PAGE_SIZE)
  82. #define CONFIG_SYS_NAND_5_ADDR_CYCLE
  83. /* NAND: driver related configs */
  84. #define CONFIG_SYS_NAND_ONFI_DETECTION
  85. #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
  86. #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
  87. #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
  88. 10, 11, 12, 13, 14, 15, 16, 17, \
  89. 18, 19, 20, 21, 22, 23, 24, 25, \
  90. 26, 27, 28, 29, 30, 31, 32, 33, \
  91. 34, 35, 36, 37, 38, 39, 40, 41, \
  92. 42, 43, 44, 45, 46, 47, 48, 49, \
  93. 50, 51, 52, 53, 54, 55, 56, 57, }
  94. #define CONFIG_SYS_NAND_ECCSIZE 512
  95. #define CONFIG_SYS_NAND_ECCBYTES 14
  96. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00140000
  97. /* NAND: SPL related configs */
  98. /* NAND: SPL falcon mode configs */
  99. #ifdef CONFIG_SPL_OS_BOOT
  100. #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */
  101. #endif
  102. #endif /* !CONFIG_MTD_RAW_NAND */
  103. /* Parallel NOR Support */
  104. #if defined(CONFIG_NOR)
  105. /* NOR: device related configs */
  106. #define CONFIG_SYS_MAX_FLASH_SECT 512
  107. #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  108. #define CONFIG_SYS_FLASH_SIZE (64 * 1024 * 1024) /* 64 MB */
  109. /* #define CONFIG_INIT_IGNORE_ERROR */
  110. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  111. #define CONFIG_SYS_FLASH_BASE (0x08000000)
  112. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  113. /* Reduce SPL size by removing unlikey targets */
  114. #endif /* NOR support */
  115. #endif /* __CONFIG_DRA7XX_EVM_H */