da850evm.h 7.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
  4. *
  5. * Based on davinci_dvevm.h. Original Copyrights follow:
  6. *
  7. * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
  8. */
  9. #ifndef __CONFIG_H
  10. #define __CONFIG_H
  11. /*
  12. * Board
  13. */
  14. /* check if direct NOR boot config is used */
  15. #ifndef CONFIG_DIRECT_NOR_BOOT
  16. #define CONFIG_USE_SPIFLASH
  17. #endif
  18. /*
  19. * SoC Configuration
  20. */
  21. #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
  22. #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
  23. #define CONFIG_SYS_OSCIN_FREQ 24000000
  24. #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
  25. #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
  26. #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
  27. #ifdef CONFIG_DIRECT_NOR_BOOT
  28. #define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
  29. #endif
  30. /*
  31. * Memory Info
  32. */
  33. #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
  34. #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
  35. #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
  36. #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
  37. #define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE
  38. #define CONFIG_SPL_BSS_MAX_SIZE 0x1080000
  39. /* memtest start addr */
  40. #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
  41. /* memtest will be run on 16MB */
  42. #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
  43. #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
  44. DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
  45. DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
  46. DAVINCI_SYSCFG_SUSPSRC_UART2 | \
  47. DAVINCI_SYSCFG_SUSPSRC_EMAC | \
  48. DAVINCI_SYSCFG_SUSPSRC_I2C)
  49. /*
  50. * PLL configuration
  51. */
  52. #define CONFIG_SYS_DA850_PLL0_PLLM 24
  53. #define CONFIG_SYS_DA850_PLL1_PLLM 21
  54. /*
  55. * DDR2 memory configuration
  56. */
  57. #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
  58. DV_DDR_PHY_EXT_STRBEN | \
  59. (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
  60. #define CONFIG_SYS_DA850_DDR2_SDBCR ( \
  61. (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \
  62. (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
  63. (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
  64. (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
  65. (0x3 << DV_DDR_SDCR_CL_SHIFT) | \
  66. (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \
  67. (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
  68. /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
  69. #define CONFIG_SYS_DA850_DDR2_SDBCR2 0
  70. #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
  71. (14 << DV_DDR_SDTMR1_RFC_SHIFT) | \
  72. (2 << DV_DDR_SDTMR1_RP_SHIFT) | \
  73. (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \
  74. (1 << DV_DDR_SDTMR1_WR_SHIFT) | \
  75. (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
  76. (8 << DV_DDR_SDTMR1_RC_SHIFT) | \
  77. (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
  78. (0 << DV_DDR_SDTMR1_WTR_SHIFT))
  79. #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
  80. (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
  81. (0 << DV_DDR_SDTMR2_XP_SHIFT) | \
  82. (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
  83. (17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
  84. (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
  85. (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \
  86. (0 << DV_DDR_SDTMR2_CKE_SHIFT))
  87. #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494
  88. #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
  89. /*
  90. * Serial Driver info
  91. */
  92. #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
  93. #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
  94. #ifdef CONFIG_USE_SPIFLASH
  95. #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
  96. #endif
  97. /*
  98. * I2C Configuration
  99. */
  100. #ifndef CONFIG_SPL_BUILD
  101. #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
  102. #endif
  103. /*
  104. * Flash & Environment
  105. */
  106. #ifdef CONFIG_MTD_RAW_NAND
  107. #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
  108. #define CONFIG_SYS_NAND_PAGE_2K
  109. #define CONFIG_SYS_NAND_CS 3
  110. #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
  111. #define CONFIG_SYS_NAND_MASK_CLE 0x10
  112. #define CONFIG_SYS_NAND_MASK_ALE 0x8
  113. #undef CONFIG_SYS_NAND_HW_ECC
  114. #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
  115. #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
  116. #define CONFIG_SYS_NAND_5_ADDR_CYCLE
  117. #define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
  118. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
  119. #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000
  120. #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
  121. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
  122. #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
  123. CONFIG_SYS_NAND_U_BOOT_SIZE - \
  124. CONFIG_SYS_MALLOC_LEN - \
  125. GENERATED_GBL_DATA_SIZE)
  126. #define CONFIG_SYS_NAND_ECCPOS { \
  127. 24, 25, 26, 27, 28, \
  128. 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
  129. 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
  130. 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
  131. 59, 60, 61, 62, 63 }
  132. #define CONFIG_SYS_NAND_PAGE_COUNT 64
  133. #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
  134. #define CONFIG_SYS_NAND_ECCSIZE 512
  135. #define CONFIG_SYS_NAND_ECCBYTES 10
  136. #define CONFIG_SYS_NAND_OOBSIZE 64
  137. #define CONFIG_SPL_NAND_BASE
  138. #define CONFIG_SPL_NAND_DRIVERS
  139. #define CONFIG_SPL_NAND_ECC
  140. #define CONFIG_SPL_NAND_LOAD
  141. #ifndef CONFIG_SPL_BUILD
  142. #define CONFIG_SYS_NAND_SELF_INIT
  143. #endif
  144. #endif
  145. /*
  146. * Network & Ethernet Configuration
  147. */
  148. #ifdef CONFIG_DRIVER_TI_EMAC
  149. #define CONFIG_BOOTP_DNS2
  150. #define CONFIG_BOOTP_SEND_HOSTNAME
  151. #define CONFIG_NET_RETRY_COUNT 10
  152. #endif
  153. #ifdef CONFIG_USE_NOR
  154. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
  155. #define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */
  156. #define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
  157. #define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */
  158. #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
  159. + 3)
  160. #endif
  161. /*
  162. * U-Boot general configuration
  163. */
  164. #define CONFIG_BOOTFILE "uImage" /* Boot file name */
  165. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  166. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
  167. #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
  168. /*
  169. * Linux Information
  170. */
  171. #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
  172. #define CONFIG_HWCONFIG /* enable hwconfig */
  173. #define CONFIG_CMDLINE_TAG
  174. #define CONFIG_REVISION_TAG
  175. #define CONFIG_SETUP_MEMORY_TAGS
  176. #define CONFIG_BOOTCOMMAND \
  177. "run envboot; " \
  178. "run mmcboot; "
  179. #define DEFAULT_LINUX_BOOT_ENV \
  180. "loadaddr=0xc0700000\0" \
  181. "fdtaddr=0xc0600000\0" \
  182. "scriptaddr=0xc0600000\0"
  183. #include <environment/ti/mmc.h>
  184. #define CONFIG_EXTRA_ENV_SETTINGS \
  185. DEFAULT_LINUX_BOOT_ENV \
  186. DEFAULT_MMC_TI_ARGS \
  187. "bootpart=0:2\0" \
  188. "bootdir=/boot\0" \
  189. "bootfile=zImage\0" \
  190. "fdtfile=da850-evm.dtb\0" \
  191. "boot_fdt=yes\0" \
  192. "boot_fit=0\0" \
  193. "console=ttyS2,115200n8\0" \
  194. "hwconfig=dsp:wake=yes"
  195. #ifdef CONFIG_CMD_BDI
  196. #define CONFIG_CLOCKS
  197. #endif
  198. #if !defined(CONFIG_MTD_RAW_NAND) && \
  199. !defined(CONFIG_USE_NOR) && \
  200. !defined(CONFIG_USE_SPIFLASH)
  201. #endif
  202. /* USB Configs */
  203. #define CONFIG_USB_OHCI_NEW
  204. #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
  205. #ifndef CONFIG_DIRECT_NOR_BOOT
  206. /* defines for SPL */
  207. #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
  208. CONFIG_SYS_MALLOC_LEN)
  209. #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
  210. #define CONFIG_SPL_STACK 0x8001ff00
  211. #define CONFIG_SPL_MAX_FOOTPRINT 32768
  212. #define CONFIG_SPL_PAD_TO 32768
  213. #endif
  214. /* Load U-Boot Image From MMC */
  215. /* additions for new relocation code, must added to all boards */
  216. #define CONFIG_SYS_SDRAM_BASE 0xc0000000
  217. #ifdef CONFIG_DIRECT_NOR_BOOT
  218. #define CONFIG_SYS_INIT_SP_ADDR 0x8001ff00
  219. #else
  220. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
  221. GENERATED_GBL_DATA_SIZE)
  222. #endif /* CONFIG_DIRECT_NOR_BOOT */
  223. #include <asm/arch/hardware.h>
  224. #endif /* __CONFIG_H */