corvus.h 4.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Common board functions for siemens AT91SAM9G45 based boards
  4. * (C) Copyright 2013 Siemens AG
  5. *
  6. * Based on:
  7. * U-Boot file: include/configs/at91sam9m10g45ek.h
  8. * (C) Copyright 2007-2008
  9. * Stelian Pop <stelian@popies.net>
  10. * Lead Tech Design <www.leadtechdesign.com>
  11. */
  12. #ifndef __CONFIG_H
  13. #define __CONFIG_H
  14. #include <asm/hardware.h>
  15. #include <linux/sizes.h>
  16. /*
  17. * Warning: changing CONFIG_SYS_TEXT_BASE requires
  18. * adapting the initial boot program.
  19. * Since the linker has to swallow that define, we must use a pure
  20. * hex number here!
  21. */
  22. #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
  23. /* ARM asynchronous clock */
  24. #define CONFIG_SYS_AT91_SLOW_CLOCK 32768
  25. #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
  26. #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
  27. #define CONFIG_SETUP_MEMORY_TAGS
  28. #define CONFIG_INITRD_TAG
  29. #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
  30. /* general purpose I/O */
  31. #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
  32. #define CONFIG_AT91_GPIO
  33. #define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */
  34. /* serial console */
  35. #define CONFIG_USART_BASE ATMEL_BASE_DBGU
  36. #define CONFIG_USART_ID ATMEL_ID_SYS
  37. /* LED */
  38. #define CONFIG_AT91_LED
  39. #define CONFIG_RED_LED AT91_PIN_PD31 /* this is the user1 led */
  40. #define CONFIG_GREEN_LED AT91_PIN_PD0 /* this is the user2 led */
  41. /*
  42. * BOOTP options
  43. */
  44. #define CONFIG_BOOTP_BOOTFILESIZE
  45. /* SDRAM */
  46. #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6
  47. #define CONFIG_SYS_SDRAM_SIZE 0x08000000
  48. #define CONFIG_SYS_INIT_SP_ADDR \
  49. (CONFIG_SYS_SDRAM_BASE + SZ_32K - GENERATED_GBL_DATA_SIZE)
  50. /* NAND flash */
  51. #ifdef CONFIG_CMD_NAND
  52. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  53. #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
  54. #define CONFIG_SYS_NAND_DBW_8
  55. /* our ALE is AD21 */
  56. #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
  57. /* our CLE is AD22 */
  58. #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
  59. #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
  60. #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8
  61. #define CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT
  62. #endif
  63. /* Ethernet */
  64. #define CONFIG_MACB
  65. #define CONFIG_RMII
  66. #define CONFIG_NET_RETRY_COUNT 20
  67. #define CONFIG_AT91_WANTS_COMMON_PHY
  68. /* DFU class support */
  69. #define CONFIG_SYS_DFU_DATA_BUF_SIZE (SZ_1M)
  70. #define DFU_MANIFEST_POLL_TIMEOUT 25000
  71. #define CONFIG_SYS_LOAD_ADDR ATMEL_BASE_CS6
  72. /* bootstrap + u-boot + env in nandflash */
  73. #define CONFIG_BOOTCOMMAND \
  74. "nand read 0x70000000 0x200000 0x300000;" \
  75. "bootm 0x70000000"
  76. /*
  77. * Size of malloc() pool
  78. */
  79. #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \
  80. SZ_4M, 0x1000)
  81. /* Defines for SPL */
  82. #define CONFIG_SPL_MAX_SIZE (12 * SZ_1K)
  83. #define CONFIG_SPL_STACK (SZ_16K)
  84. #define CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_MAX_SIZE
  85. #define CONFIG_SPL_BSS_MAX_SIZE (SZ_2K)
  86. #define CONFIG_SPL_NAND_DRIVERS
  87. #define CONFIG_SPL_NAND_BASE
  88. #define CONFIG_SPL_NAND_ECC
  89. #define CONFIG_SPL_NAND_RAW_ONLY
  90. #define CONFIG_SPL_NAND_SOFTECC
  91. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
  92. #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
  93. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
  94. #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
  95. #define CONFIG_SYS_NAND_5_ADDR_CYCLE
  96. #define CONFIG_SYS_NAND_PAGE_SIZE SZ_2K
  97. #define CONFIG_SYS_NAND_BLOCK_SIZE (SZ_128K)
  98. #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
  99. CONFIG_SYS_NAND_PAGE_SIZE)
  100. #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
  101. #define CONFIG_SYS_NAND_ECCSIZE 256
  102. #define CONFIG_SYS_NAND_ECCBYTES 3
  103. #define CONFIG_SYS_NAND_OOBSIZE 64
  104. #define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
  105. 48, 49, 50, 51, 52, 53, 54, 55, \
  106. 56, 57, 58, 59, 60, 61, 62, 63, }
  107. #define CONFIG_SPL_ATMEL_SIZE
  108. #define CONFIG_SYS_MASTER_CLOCK 132096000
  109. #define AT91_PLL_LOCK_TIMEOUT 1000000
  110. #define CONFIG_SYS_AT91_PLLA 0x20c73f03
  111. #define CONFIG_SYS_MCKR 0x1301
  112. #define CONFIG_SYS_MCKR_CSS 0x1302
  113. #define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS
  114. #define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
  115. #endif