corenet_ds.h 20 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2009-2012 Freescale Semiconductor, Inc.
  4. */
  5. /*
  6. * Corenet DS style board configuration file
  7. */
  8. #ifndef __CONFIG_H
  9. #define __CONFIG_H
  10. #include "../board/freescale/common/ics307_clk.h"
  11. #ifdef CONFIG_RAMBOOT_PBL
  12. #ifdef CONFIG_NXP_ESBC
  13. #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
  14. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  15. #ifdef CONFIG_MTD_RAW_NAND
  16. #define CONFIG_RAMBOOT_NAND
  17. #endif
  18. #define CONFIG_BOOTSCRIPT_COPY_RAM
  19. #else
  20. #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
  21. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  22. #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
  23. #if defined(CONFIG_TARGET_P3041DS)
  24. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg
  25. #elif defined(CONFIG_TARGET_P4080DS)
  26. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg
  27. #elif defined(CONFIG_TARGET_P5020DS)
  28. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg
  29. #elif defined(CONFIG_TARGET_P5040DS)
  30. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg
  31. #endif
  32. #endif
  33. #endif
  34. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  35. /* Set 1M boot space */
  36. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  37. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  38. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  39. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  40. #endif
  41. /* High Level Configuration Options */
  42. #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  43. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  44. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  45. #endif
  46. #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  47. #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  48. #define CONFIG_PCIE1 /* PCIE controller 1 */
  49. #define CONFIG_PCIE2 /* PCIE controller 2 */
  50. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  51. #define CONFIG_ENV_OVERWRITE
  52. #if defined(CONFIG_SPIFLASH)
  53. #elif defined(CONFIG_SDCARD)
  54. #define CONFIG_FSL_FIXED_MMC_LOCATION
  55. #define CONFIG_SYS_MMC_ENV_DEV 0
  56. #endif
  57. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
  58. /*
  59. * These can be toggled for performance analysis, otherwise use default.
  60. */
  61. #define CONFIG_SYS_CACHE_STASHING
  62. #define CONFIG_BACKSIDE_L2_CACHE
  63. #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
  64. #define CONFIG_BTB /* toggle branch predition */
  65. #define CONFIG_DDR_ECC
  66. #ifdef CONFIG_DDR_ECC
  67. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  68. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  69. #endif
  70. #define CONFIG_ENABLE_36BIT_PHYS
  71. #ifdef CONFIG_PHYS_64BIT
  72. #define CONFIG_ADDR_MAP
  73. #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
  74. #endif
  75. #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
  76. #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
  77. #define CONFIG_SYS_MEMTEST_END 0x00400000
  78. /*
  79. * Config the L3 Cache as L3 SRAM
  80. */
  81. #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
  82. #ifdef CONFIG_PHYS_64BIT
  83. #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
  84. #else
  85. #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
  86. #endif
  87. #define CONFIG_SYS_L3_SIZE (1024 << 10)
  88. #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
  89. #ifdef CONFIG_PHYS_64BIT
  90. #define CONFIG_SYS_DCSRBAR 0xf0000000
  91. #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  92. #endif
  93. /* EEPROM */
  94. #define CONFIG_ID_EEPROM
  95. #define CONFIG_SYS_I2C_EEPROM_NXID
  96. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  97. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  98. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  99. /*
  100. * DDR Setup
  101. */
  102. #define CONFIG_VERY_BIG_RAM
  103. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  104. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  105. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  106. #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
  107. #define CONFIG_DDR_SPD
  108. #define CONFIG_SYS_SPD_BUS_NUM 1
  109. #define SPD_EEPROM_ADDRESS1 0x51
  110. #define SPD_EEPROM_ADDRESS2 0x52
  111. #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
  112. #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
  113. /*
  114. * Local Bus Definitions
  115. */
  116. /* Set the local bus clock 1/8 of platform clock */
  117. #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
  118. #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */
  119. #ifdef CONFIG_PHYS_64BIT
  120. #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
  121. #else
  122. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  123. #endif
  124. #define CONFIG_SYS_FLASH_BR_PRELIM \
  125. (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
  126. | BR_PS_16 | BR_V)
  127. #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
  128. | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
  129. #define CONFIG_SYS_BR1_PRELIM \
  130. (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
  131. #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
  132. #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
  133. #ifdef CONFIG_PHYS_64BIT
  134. #define PIXIS_BASE_PHYS 0xfffdf0000ull
  135. #else
  136. #define PIXIS_BASE_PHYS PIXIS_BASE
  137. #endif
  138. #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
  139. #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
  140. #define PIXIS_LBMAP_SWITCH 7
  141. #define PIXIS_LBMAP_MASK 0xf0
  142. #define PIXIS_LBMAP_SHIFT 4
  143. #define PIXIS_LBMAP_ALTBANK 0x40
  144. #define CONFIG_SYS_FLASH_QUIET_TEST
  145. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  146. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  147. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  148. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  149. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  150. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  151. #if defined(CONFIG_RAMBOOT_PBL)
  152. #define CONFIG_SYS_RAMBOOT
  153. #endif
  154. /* Nand Flash */
  155. #ifdef CONFIG_NAND_FSL_ELBC
  156. #define CONFIG_SYS_NAND_BASE 0xffa00000
  157. #ifdef CONFIG_PHYS_64BIT
  158. #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
  159. #else
  160. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  161. #endif
  162. #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
  163. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  164. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  165. /* NAND flash config */
  166. #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  167. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  168. | BR_PS_8 /* Port Size = 8 bit */ \
  169. | BR_MS_FCM /* MSEL = FCM */ \
  170. | BR_V) /* valid */
  171. #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
  172. | OR_FCM_PGS /* Large Page*/ \
  173. | OR_FCM_CSCT \
  174. | OR_FCM_CST \
  175. | OR_FCM_CHT \
  176. | OR_FCM_SCY_1 \
  177. | OR_FCM_TRLX \
  178. | OR_FCM_EHTR)
  179. #ifdef CONFIG_MTD_RAW_NAND
  180. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
  181. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  182. #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
  183. #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
  184. #else
  185. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
  186. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
  187. #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
  188. #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  189. #endif
  190. #else
  191. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
  192. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
  193. #endif /* CONFIG_NAND_FSL_ELBC */
  194. #define CONFIG_SYS_FLASH_EMPTY_INFO
  195. #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
  196. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
  197. #define CONFIG_HWCONFIG
  198. /* define to use L1 as initial stack */
  199. #define CONFIG_L1_INIT_RAM
  200. #define CONFIG_SYS_INIT_RAM_LOCK
  201. #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
  202. #ifdef CONFIG_PHYS_64BIT
  203. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  204. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
  205. /* The assembler doesn't like typecast */
  206. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  207. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  208. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  209. #else
  210. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
  211. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
  212. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
  213. #endif
  214. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
  215. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  216. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  217. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  218. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
  219. /* Serial Port - controlled on board with jumper J8
  220. * open - index 2
  221. * shorted - index 1
  222. */
  223. #define CONFIG_SYS_NS16550_SERIAL
  224. #define CONFIG_SYS_NS16550_REG_SIZE 1
  225. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  226. #define CONFIG_SYS_BAUDRATE_TABLE \
  227. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  228. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
  229. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
  230. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
  231. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
  232. /* I2C */
  233. #define CONFIG_SYS_I2C
  234. #define CONFIG_SYS_I2C_FSL
  235. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  236. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  237. #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
  238. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  239. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  240. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
  241. /*
  242. * RapidIO
  243. */
  244. #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
  245. #ifdef CONFIG_PHYS_64BIT
  246. #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
  247. #else
  248. #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
  249. #endif
  250. #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
  251. #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
  252. #ifdef CONFIG_PHYS_64BIT
  253. #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
  254. #else
  255. #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
  256. #endif
  257. #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
  258. /*
  259. * for slave u-boot IMAGE instored in master memory space,
  260. * PHYS must be aligned based on the SIZE
  261. */
  262. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
  263. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
  264. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
  265. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
  266. /*
  267. * for slave UCODE and ENV instored in master memory space,
  268. * PHYS must be aligned based on the SIZE
  269. */
  270. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
  271. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
  272. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
  273. /* slave core release by master*/
  274. #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
  275. #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
  276. /*
  277. * SRIO_PCIE_BOOT - SLAVE
  278. */
  279. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  280. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
  281. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
  282. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
  283. #endif
  284. /*
  285. * eSPI - Enhanced SPI
  286. */
  287. /*
  288. * General PCI
  289. * Memory space is mapped 1-1, but I/O space must start from 0.
  290. */
  291. /* controller 1, direct to uli, tgtid 3, Base address 20000 */
  292. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  293. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  294. #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  295. #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  296. /* controller 2, Slot 2, tgtid 2, Base address 201000 */
  297. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  298. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  299. #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
  300. #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
  301. /* controller 3, Slot 1, tgtid 1, Base address 202000 */
  302. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
  303. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
  304. #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
  305. #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
  306. /* controller 4, Base address 203000 */
  307. #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
  308. #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
  309. /* Qman/Bman */
  310. #define CONFIG_SYS_BMAN_NUM_PORTALS 10
  311. #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  312. #ifdef CONFIG_PHYS_64BIT
  313. #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  314. #else
  315. #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
  316. #endif
  317. #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
  318. #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
  319. #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
  320. #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
  321. #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  322. #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
  323. CONFIG_SYS_BMAN_CENA_SIZE)
  324. #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  325. #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
  326. #define CONFIG_SYS_QMAN_NUM_PORTALS 10
  327. #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
  328. #ifdef CONFIG_PHYS_64BIT
  329. #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
  330. #else
  331. #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
  332. #endif
  333. #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
  334. #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
  335. #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
  336. #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
  337. #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  338. #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
  339. CONFIG_SYS_QMAN_CENA_SIZE)
  340. #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  341. #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
  342. #define CONFIG_SYS_DPAA_FMAN
  343. #define CONFIG_SYS_DPAA_PME
  344. /* Default address of microcode for the Linux Fman driver */
  345. #if defined(CONFIG_SPIFLASH)
  346. /*
  347. * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  348. * env, so we got 0x110000.
  349. */
  350. #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
  351. #elif defined(CONFIG_SDCARD)
  352. /*
  353. * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  354. * about 825KB (1650 blocks), Env is stored after the image, and the env size is
  355. * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
  356. */
  357. #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
  358. #elif defined(CONFIG_MTD_RAW_NAND)
  359. #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
  360. #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  361. /*
  362. * Slave has no ucode locally, it can fetch this from remote. When implementing
  363. * in two corenet boards, slave's ucode could be stored in master's memory
  364. * space, the address can be mapped from slave TLB->slave LAW->
  365. * slave SRIO or PCIE outbound window->master inbound window->
  366. * master LAW->the ucode address in master's memory space.
  367. */
  368. #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
  369. #else
  370. #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
  371. #endif
  372. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  373. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  374. #ifdef CONFIG_SYS_DPAA_FMAN
  375. #define CONFIG_PHYLIB_10G
  376. #define CONFIG_PHY_VITESSE
  377. #define CONFIG_PHY_TERANETICS
  378. #endif
  379. #ifdef CONFIG_PCI
  380. #if !defined(CONFIG_DM_PCI)
  381. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  382. #define CONFIG_PCI_INDIRECT_BRIDGE
  383. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  384. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  385. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  386. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  387. #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
  388. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
  389. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  390. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  391. #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  392. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
  393. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  394. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  395. #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
  396. #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
  397. #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
  398. #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
  399. #endif
  400. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  401. #endif /* CONFIG_PCI */
  402. /* SATA */
  403. #ifdef CONFIG_FSL_SATA_V2
  404. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  405. #define CONFIG_SATA1
  406. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  407. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  408. #define CONFIG_SATA2
  409. #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  410. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  411. #define CONFIG_LBA48
  412. #endif
  413. #ifdef CONFIG_FMAN_ENET
  414. #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c
  415. #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d
  416. #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e
  417. #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f
  418. #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4
  419. #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c
  420. #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d
  421. #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e
  422. #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f
  423. #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0
  424. #define CONFIG_SYS_TBIPA_VALUE 8
  425. #define CONFIG_ETHPRIME "FM1@DTSEC1"
  426. #endif
  427. /*
  428. * Environment
  429. */
  430. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  431. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  432. /*
  433. * USB
  434. */
  435. #define CONFIG_HAS_FSL_DR_USB
  436. #define CONFIG_HAS_FSL_MPH_USB
  437. #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
  438. #define CONFIG_USB_EHCI_FSL
  439. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  440. #endif
  441. #ifdef CONFIG_MMC
  442. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  443. #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
  444. #endif
  445. /*
  446. * Miscellaneous configurable options
  447. */
  448. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  449. /*
  450. * For booting Linux, the board info and command line data
  451. * have to be in the first 64 MB of memory, since this is
  452. * the maximum mapped by the Linux kernel during initialization.
  453. */
  454. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
  455. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  456. #ifdef CONFIG_CMD_KGDB
  457. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  458. #endif
  459. /*
  460. * Environment Configuration
  461. */
  462. #define CONFIG_ROOTPATH "/opt/nfsroot"
  463. #define CONFIG_BOOTFILE "uImage"
  464. #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
  465. /* default location for tftp and bootm */
  466. #define CONFIG_LOADADDR 1000000
  467. #ifdef CONFIG_TARGET_P4080DS
  468. #define __USB_PHY_TYPE ulpi
  469. #else
  470. #define __USB_PHY_TYPE utmi
  471. #endif
  472. #define CONFIG_EXTRA_ENV_SETTINGS \
  473. "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
  474. "bank_intlv=cs0_cs1;" \
  475. "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
  476. "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
  477. "netdev=eth0\0" \
  478. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  479. "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  480. "tftpflash=tftpboot $loadaddr $uboot && " \
  481. "protect off $ubootaddr +$filesize && " \
  482. "erase $ubootaddr +$filesize && " \
  483. "cp.b $loadaddr $ubootaddr $filesize && " \
  484. "protect on $ubootaddr +$filesize && " \
  485. "cmp.b $loadaddr $ubootaddr $filesize\0" \
  486. "consoledev=ttyS0\0" \
  487. "ramdiskaddr=2000000\0" \
  488. "ramdiskfile=p4080ds/ramdisk.uboot\0" \
  489. "fdtaddr=1e00000\0" \
  490. "fdtfile=p4080ds/p4080ds.dtb\0" \
  491. "bdev=sda3\0"
  492. #define CONFIG_HDBOOT \
  493. "setenv bootargs root=/dev/$bdev rw " \
  494. "console=$consoledev,$baudrate $othbootargs;" \
  495. "tftp $loadaddr $bootfile;" \
  496. "tftp $fdtaddr $fdtfile;" \
  497. "bootm $loadaddr - $fdtaddr"
  498. #define CONFIG_NFSBOOTCOMMAND \
  499. "setenv bootargs root=/dev/nfs rw " \
  500. "nfsroot=$serverip:$rootpath " \
  501. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  502. "console=$consoledev,$baudrate $othbootargs;" \
  503. "tftp $loadaddr $bootfile;" \
  504. "tftp $fdtaddr $fdtfile;" \
  505. "bootm $loadaddr - $fdtaddr"
  506. #define CONFIG_RAMBOOTCOMMAND \
  507. "setenv bootargs root=/dev/ram rw " \
  508. "console=$consoledev,$baudrate $othbootargs;" \
  509. "tftp $ramdiskaddr $ramdiskfile;" \
  510. "tftp $loadaddr $bootfile;" \
  511. "tftp $fdtaddr $fdtfile;" \
  512. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  513. #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
  514. #include <asm/fsl_secure_boot.h>
  515. #endif /* __CONFIG_H */