controlcenterdc.h 5.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2014 Stefan Roese <sr@denx.de>
  4. * Copyright (C) 2016 Mario Six <mario.six@gdsys.cc>
  5. */
  6. #ifndef _CONFIG_CONTROLCENTERDC_H
  7. #define _CONFIG_CONTROLCENTERDC_H
  8. /*
  9. * High Level Configuration Options (easy to change)
  10. */
  11. #define CONFIG_CUSTOMER_BOARD_SUPPORT
  12. #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
  13. #define CONFIG_BOARD_LATE_INIT
  14. /*
  15. * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
  16. * for DDR ECC byte filling in the SPL before loading the main
  17. * U-Boot into it.
  18. */
  19. #define CONFIG_SYS_TCLK 250000000 /* 250MHz */
  20. #define CONFIG_LOADADDR 1000000
  21. /*
  22. * SDIO/MMC Card Configuration
  23. */
  24. #define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE
  25. /*
  26. * SATA/SCSI/AHCI configuration
  27. */
  28. #define CONFIG_SCSI_AHCI_PLAT
  29. #define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
  30. #define CONFIG_SYS_SCSI_MAX_LUN 1
  31. #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
  32. CONFIG_SYS_SCSI_MAX_LUN)
  33. /* USB/EHCI configuration */
  34. #define CONFIG_EHCI_IS_TDI
  35. /* Environment in SPI NOR flash */
  36. #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
  37. /* PCIe support */
  38. #ifndef CONFIG_SPL_BUILD
  39. #define CONFIG_PCI_SCAN_SHOW
  40. #endif
  41. /*
  42. * Software (bit-bang) MII driver configuration
  43. */
  44. #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
  45. #define CONFIG_BITBANGMII_MULTI
  46. /* SPL */
  47. /*
  48. * Select the boot device here
  49. *
  50. * Currently supported are:
  51. * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash
  52. * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1)
  53. */
  54. #define SPL_BOOT_SPI_NOR_FLASH 1
  55. #define SPL_BOOT_SDIO_MMC_CARD 2
  56. #define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH
  57. /* Defines for SPL */
  58. #define CONFIG_SPL_SIZE (160 << 10)
  59. #if defined(CONFIG_SECURED_MODE_IMAGE)
  60. #define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x2614)
  61. #else
  62. #define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x30)
  63. #endif
  64. #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE)
  65. #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
  66. #ifdef CONFIG_SPL_BUILD
  67. #define CONFIG_SYS_MALLOC_SIMPLE
  68. #endif
  69. #define CONFIG_SPL_STACK (0x40000000 + ((212 - 16) << 10))
  70. #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
  71. #define CONFIG_SPL_LIBCOMMON_SUPPORT
  72. #define CONFIG_SPL_LIBGENERIC_SUPPORT
  73. #define CONFIG_SPL_I2C_SUPPORT
  74. #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
  75. /* SPL related SPI defines */
  76. #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
  77. #endif
  78. #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD
  79. /* SPL related MMC defines */
  80. #define CONFIG_SPL_MMC_SUPPORT
  81. #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
  82. #define CONFIG_SYS_MMC_U_BOOT_OFFS (168 << 10)
  83. #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS
  84. #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR (CONFIG_SYS_U_BOOT_OFFS / 512)
  85. #ifdef CONFIG_SPL_BUILD
  86. #define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */
  87. #endif
  88. #endif
  89. /*
  90. * Environment Configuration
  91. */
  92. #define CONFIG_ENV_OVERWRITE
  93. #define CONFIG_BAUDRATE 115200
  94. #define CONFIG_HOSTNAME "ccdc"
  95. #define CONFIG_ROOTPATH "/opt/nfsroot"
  96. #define CONFIG_BOOTFILE "ccdc.img"
  97. #define CONFIG_EXTRA_ENV_SETTINGS \
  98. "netdev=eth1\0" \
  99. "consoledev=ttyS1\0" \
  100. "u-boot=u-boot.bin\0" \
  101. "bootfile_addr=1000000\0" \
  102. "keyprogram_addr=3000000\0" \
  103. "keyprogram_file=keyprogram.img\0" \
  104. "fdtfile=controlcenterdc.dtb\0" \
  105. "load=tftpboot ${loadaddr} ${u-boot}\0" \
  106. "mmcdev=0:2\0" \
  107. "update=sf probe 1:0;" \
  108. " sf erase 0 +${filesize};" \
  109. " sf write ${fileaddr} 0 ${filesize}\0" \
  110. "upd=run load update\0" \
  111. "fdt_high=0x10000000\0" \
  112. "initrd_high=0x10000000\0" \
  113. "loadkeyprogram=tpm flush_keys;" \
  114. " mmc rescan;" \
  115. " ext4load mmc ${mmcdev} ${keyprogram_addr} ${keyprogram_file};"\
  116. " source ${keyprogram_addr}:script@1\0" \
  117. "gpio1=gpio@22_25\0" \
  118. "gpio2=A29\0" \
  119. "blinkseq='0 0 0 0 2 0 2 2 3 1 3 1 0 0 2 2 3 1 3 3 2 0 2 2 3 1 1 1 " \
  120. "2 0 2 2 3 1 3 1 0 0 2 0 3 3 3 1 2 0 0 0 3 1 1 1 0 0 0 0'\0" \
  121. "bootfail=for i in ${blinkseq}; do" \
  122. " if test $i -eq 0; then" \
  123. " gpio clear ${gpio1}; gpio set ${gpio2};" \
  124. " elif test $i -eq 1; then" \
  125. " gpio clear ${gpio1}; gpio clear ${gpio2};" \
  126. " elif test $i -eq 2; then" \
  127. " gpio set ${gpio1}; gpio set ${gpio2};" \
  128. " else;" \
  129. " gpio clear ${gpio1}; gpio set ${gpio2};" \
  130. " fi; sleep 0.12; done\0"
  131. #define CONFIG_NFSBOOTCOMMAND \
  132. "setenv bootargs root=/dev/nfs rw " \
  133. "nfsroot=${serverip}:${rootpath} " \
  134. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off " \
  135. "console=${consoledev},${baudrate} ${othbootargs}; " \
  136. "tftpboot ${bootfile_addr} ${bootfile}; " \
  137. "bootm ${bootfile_addr}"
  138. #define CONFIG_MMCBOOTCOMMAND \
  139. "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
  140. "console=${consoledev},${baudrate} ${othbootargs}; " \
  141. "ext2load mmc 0:2 ${bootfile_addr} ${bootfile}; " \
  142. "bootm ${bootfile_addr}"
  143. #define CONFIG_BOOTCOMMAND \
  144. "if env exists keyprogram; then;" \
  145. " setenv keyprogram; run nfsboot;" \
  146. " fi;" \
  147. " run dobootfail"
  148. /*
  149. * mv-common.h should be defined after CMD configs since it used them
  150. * to enable certain macros
  151. */
  152. #include "mv-common.h"
  153. #endif /* _CONFIG_CONTROLCENTERDC_H */