colibri_pxa270.h 4.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Toradex Colibri PXA270 configuration file
  4. *
  5. * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
  6. * Copyright (C) 2015-2016 Marcel Ziswiler <marcel@ziswiler.com>
  7. */
  8. #ifndef __CONFIG_H
  9. #define __CONFIG_H
  10. /*
  11. * High Level Board Configuration Options
  12. */
  13. #define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
  14. /* Avoid overwriting factory configuration block */
  15. #define CONFIG_BOARD_SIZE_LIMIT 0x40000
  16. /*
  17. * Environment settings
  18. */
  19. #define CONFIG_ENV_OVERWRITE
  20. #define CONFIG_SYS_MALLOC_LEN (128 * 1024)
  21. #define CONFIG_BOOTCOMMAND \
  22. "if fatload mmc 0 0xa0000000 uImage; then " \
  23. "bootm 0xa0000000; " \
  24. "fi; " \
  25. "if usb reset && fatload usb 0 0xa0000000 uImage; then " \
  26. "bootm 0xa0000000; " \
  27. "fi; " \
  28. "bootm 0xc0000;"
  29. #define CONFIG_TIMESTAMP
  30. #define CONFIG_CMDLINE_TAG
  31. #define CONFIG_SETUP_MEMORY_TAGS
  32. /*
  33. * Serial Console Configuration
  34. */
  35. /*
  36. * Bootloader Components Configuration
  37. */
  38. /* I2C support */
  39. #ifdef CONFIG_SYS_I2C
  40. #define CONFIG_SYS_I2C_PXA
  41. #define CONFIG_PXA_STD_I2C
  42. #define CONFIG_PXA_PWR_I2C
  43. #define CONFIG_SYS_I2C_SPEED 100000
  44. #endif
  45. /* LCD support */
  46. #ifdef CONFIG_LCD
  47. #define CONFIG_PXA_LCD
  48. #define CONFIG_PXA_VGA
  49. #define CONFIG_LCD_LOGO
  50. #endif
  51. /*
  52. * Networking Configuration
  53. */
  54. #ifdef CONFIG_CMD_NET
  55. #define CONFIG_DRIVER_DM9000 1
  56. #define CONFIG_DM9000_BASE 0x08000000
  57. #define DM9000_IO (CONFIG_DM9000_BASE)
  58. #define DM9000_DATA (CONFIG_DM9000_BASE + 4)
  59. #define CONFIG_NET_RETRY_COUNT 10
  60. #define CONFIG_BOOTP_BOOTFILESIZE
  61. #endif
  62. #define CONFIG_SYS_DEVICE_NULLDEV 1
  63. /*
  64. * Clock Configuration
  65. */
  66. #define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */
  67. /*
  68. * DRAM Map
  69. */
  70. #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
  71. #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
  72. #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
  73. #define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */
  74. #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
  75. #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
  76. #define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1
  77. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  78. #define CONFIG_SYS_INIT_SP_ADDR 0x5c010000
  79. /*
  80. * NOR FLASH
  81. */
  82. #ifdef CONFIG_CMD_FLASH
  83. #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
  84. #define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
  85. #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
  86. #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
  87. #define CONFIG_SYS_MAX_FLASH_SECT (4 + 255)
  88. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  89. #define CONFIG_SYS_FLASH_ERASE_TOUT (25 * CONFIG_SYS_HZ)
  90. #define CONFIG_SYS_FLASH_WRITE_TOUT (25 * CONFIG_SYS_HZ)
  91. #define CONFIG_SYS_FLASH_LOCK_TOUT (25 * CONFIG_SYS_HZ)
  92. #define CONFIG_SYS_FLASH_UNLOCK_TOUT (25 * CONFIG_SYS_HZ)
  93. #endif
  94. #define CONFIG_SYS_MONITOR_BASE 0x0
  95. #define CONFIG_SYS_MONITOR_LEN 0x40000
  96. /* Skip factory configuration block */
  97. /*
  98. * GPIO settings
  99. */
  100. #define CONFIG_SYS_GPSR0_VAL 0x00000000
  101. #define CONFIG_SYS_GPSR1_VAL 0x00020000
  102. #define CONFIG_SYS_GPSR2_VAL 0x0002c000
  103. #define CONFIG_SYS_GPSR3_VAL 0x00000000
  104. #define CONFIG_SYS_GPCR0_VAL 0x00000000
  105. #define CONFIG_SYS_GPCR1_VAL 0x00000000
  106. #define CONFIG_SYS_GPCR2_VAL 0x00000000
  107. #define CONFIG_SYS_GPCR3_VAL 0x00000000
  108. #define CONFIG_SYS_GPDR0_VAL 0xc8008000
  109. #define CONFIG_SYS_GPDR1_VAL 0xfc02a981
  110. #define CONFIG_SYS_GPDR2_VAL 0x92c3ffff
  111. #define CONFIG_SYS_GPDR3_VAL 0x0061e804
  112. #define CONFIG_SYS_GAFR0_L_VAL 0x80100000
  113. #define CONFIG_SYS_GAFR0_U_VAL 0xa5c00010
  114. #define CONFIG_SYS_GAFR1_L_VAL 0x6992901a
  115. #define CONFIG_SYS_GAFR1_U_VAL 0xaaa50008
  116. #define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
  117. #define CONFIG_SYS_GAFR2_U_VAL 0x4109a002
  118. #define CONFIG_SYS_GAFR3_L_VAL 0x54000310
  119. #define CONFIG_SYS_GAFR3_U_VAL 0x00005401
  120. #define CONFIG_SYS_PSSR_VAL 0x30
  121. /*
  122. * Clock settings
  123. */
  124. #define CONFIG_SYS_CKEN 0x00500240
  125. #define CONFIG_SYS_CCCR 0x02000290
  126. /*
  127. * Memory settings
  128. */
  129. #define CONFIG_SYS_MSC0_VAL 0x9ee1c5f2
  130. #define CONFIG_SYS_MSC1_VAL 0x9ee1f994
  131. #define CONFIG_SYS_MSC2_VAL 0x9ee19ee1
  132. #define CONFIG_SYS_MDCNFG_VAL 0x090009c9
  133. #define CONFIG_SYS_MDREFR_VAL 0x2003a031
  134. #define CONFIG_SYS_MDMRS_VAL 0x00220022
  135. #define CONFIG_SYS_FLYCNFG_VAL 0x00010001
  136. #define CONFIG_SYS_SXCNFG_VAL 0x40044004
  137. /*
  138. * PCMCIA and CF Interfaces
  139. */
  140. #define CONFIG_SYS_MECR_VAL 0x00000000
  141. #define CONFIG_SYS_MCMEM0_VAL 0x00028307
  142. #define CONFIG_SYS_MCMEM1_VAL 0x00014307
  143. #define CONFIG_SYS_MCATT0_VAL 0x00038787
  144. #define CONFIG_SYS_MCATT1_VAL 0x0001c787
  145. #define CONFIG_SYS_MCIO0_VAL 0x0002830f
  146. #define CONFIG_SYS_MCIO1_VAL 0x0001430f
  147. #include "pxa-common.h"
  148. #endif /* __CONFIG_H */