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- /* SPDX-License-Identifier: GPL-2.0+ */
- /*
- * (C) Copyright 2011 CompuLab, Ltd.
- * Mike Rapoport <mike@compulab.co.il>
- * Igor Grinberg <grinberg@compulab.co.il>
- *
- * Based on omap3_beagle.h
- * (C) Copyright 2006-2008
- * Texas Instruments.
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <x0khasim@ti.com>
- *
- * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards
- */
- #ifndef __CONFIG_H
- #define __CONFIG_H
- #define CONFIG_SYS_CACHELINE_SIZE 64
- /*
- * High Level Configuration Options
- */
- #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */
- #include <asm/arch/cpu.h> /* get chip and board defs */
- #include <asm/arch/omap.h>
- /* Clock Defines */
- #define V_OSCK 26000000 /* Clock output from T2 */
- #define V_SCLK (V_OSCK >> 1)
- #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
- #define CONFIG_SETUP_MEMORY_TAGS
- #define CONFIG_INITRD_TAG
- #define CONFIG_REVISION_TAG
- #define CONFIG_SERIAL_TAG
- /*
- * Size of malloc() pool
- */
- /* Sector */
- #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
- /*
- * Hardware drivers
- */
- /*
- * NS16550 Configuration
- */
- #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
- #define CONFIG_SYS_NS16550_SERIAL
- #define CONFIG_SYS_NS16550_REG_SIZE (-4)
- #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
- /*
- * select serial console configuration
- */
- #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
- /* allow to overwrite serial and ethaddr */
- #define CONFIG_ENV_OVERWRITE
- #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
- 115200}
- /* USB device configuration */
- #define CONFIG_USB_DEVICE
- #define CONFIG_USB_TTY
- /* commands to include */
- #define CONFIG_SYS_I2C
- #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
- #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
- #define CONFIG_SYS_I2C_EEPROM_BUS 0
- #define CONFIG_I2C_MULTI_BUS
- /*
- * TWL4030
- */
- /*
- * Board NAND Info.
- */
- #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
- /* to access nand at */
- /* CS0 */
- #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
- /* devices */
- /* Environment information */
- #define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=0x82000000\0" \
- "usbtty=cdc_acm\0" \
- "console=ttyO2,115200n8\0" \
- "mpurate=500\0" \
- "vram=12M\0" \
- "dvimode=1024x768MR-16@60\0" \
- "defaultdisplay=dvi\0" \
- "mmcdev=0\0" \
- "mmcroot=/dev/mmcblk0p2 rw\0" \
- "mmcrootfstype=ext4 rootwait\0" \
- "nandroot=/dev/mtdblock4 rw\0" \
- "nandrootfstype=ubifs\0" \
- "mmcargs=setenv bootargs console=${console} " \
- "mpurate=${mpurate} " \
- "vram=${vram} " \
- "omapfb.mode=dvi:${dvimode} " \
- "omapdss.def_disp=${defaultdisplay} " \
- "root=${mmcroot} " \
- "rootfstype=${mmcrootfstype}\0" \
- "nandargs=setenv bootargs console=${console} " \
- "mpurate=${mpurate} " \
- "vram=${vram} " \
- "omapfb.mode=dvi:${dvimode} " \
- "omapdss.def_disp=${defaultdisplay} " \
- "root=${nandroot} " \
- "rootfstype=${nandrootfstype}\0" \
- "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
- "bootscript=echo Running bootscript from mmc ...; " \
- "source ${loadaddr}\0" \
- "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
- "mmcboot=echo Booting from mmc ...; " \
- "run mmcargs; " \
- "bootm ${loadaddr}\0" \
- "nandboot=echo Booting from nand ...; " \
- "run nandargs; " \
- "nand read ${loadaddr} 2a0000 400000; " \
- "bootm ${loadaddr}\0" \
- #define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loaduimage; then " \
- "run mmcboot; " \
- "else run nandboot; " \
- "fi; " \
- "fi; " \
- "else run nandboot; fi"
- /*
- * Miscellaneous configurable options
- */
- #define CONFIG_TIMESTAMP
- #define CONFIG_SYS_AUTOLOAD "no"
- #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
- /* works on */
- #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
- 0x01F00000) /* 31MB */
- #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
- /* load address */
- /*
- * OMAP3 has 12 GP timers, they can be driven by the system clock
- * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
- * This rate is divided by a local divisor.
- */
- #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
- #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
- /*-----------------------------------------------------------------------
- * Physical Memory Map
- */
- #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
- /*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
- /* **** PISMO SUPPORT *** */
- /* Monitor at start of flash */
- #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
- #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
- /* additions for new relocation code, must be added to all boards */
- #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
- #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
- #define CONFIG_SYS_INIT_RAM_SIZE 0x800
- #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
- /* Status LED */
- #define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */
- #define CONFIG_SPLASHIMAGE_GUARD
- /* Display Configuration */
- #define LCD_BPP LCD_COLOR16
- #define CONFIG_SPLASH_SCREEN
- #define CONFIG_SPLASH_SOURCE
- #define CONFIG_BMP_16BPP
- #define CONFIG_SCF0403_LCD
- /* Defines for SPL */
- #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
- #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
- #define CONFIG_SPL_NAND_BASE
- #define CONFIG_SPL_NAND_DRIVERS
- #define CONFIG_SPL_NAND_ECC
- /* NAND boot config */
- #define CONFIG_SYS_NAND_5_ADDR_CYCLE
- #define CONFIG_SYS_NAND_PAGE_COUNT 64
- #define CONFIG_SYS_NAND_PAGE_SIZE 2048
- #define CONFIG_SYS_NAND_OOBSIZE 64
- #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
- #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
- /*
- * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
- * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
- */
- #define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \
- 10, 11, 12 }
- #define CONFIG_SYS_NAND_ECCSIZE 512
- #define CONFIG_SYS_NAND_ECCBYTES 3
- #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
- #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
- #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
- #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
- CONFIG_SPL_TEXT_BASE)
- /*
- * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
- * older x-loader implementations. And move the BSS area so that it
- * doesn't overlap with TEXT_BASE.
- */
- #define CONFIG_SPL_BSS_START_ADDR 0x80100000
- #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
- #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
- #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
- /* EEPROM */
- #define CONFIG_ENV_EEPROM_IS_ON_I2C
- #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
- #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
- #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
- #define CONFIG_SYS_EEPROM_SIZE 256
- #endif /* __CONFIG_H */
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