cm_t35.h 6.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2011 CompuLab, Ltd.
  4. * Mike Rapoport <mike@compulab.co.il>
  5. * Igor Grinberg <grinberg@compulab.co.il>
  6. *
  7. * Based on omap3_beagle.h
  8. * (C) Copyright 2006-2008
  9. * Texas Instruments.
  10. * Richard Woodruff <r-woodruff2@ti.com>
  11. * Syed Mohammed Khasim <x0khasim@ti.com>
  12. *
  13. * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards
  14. */
  15. #ifndef __CONFIG_H
  16. #define __CONFIG_H
  17. #define CONFIG_SYS_CACHELINE_SIZE 64
  18. /*
  19. * High Level Configuration Options
  20. */
  21. #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */
  22. #include <asm/arch/cpu.h> /* get chip and board defs */
  23. #include <asm/arch/omap.h>
  24. /* Clock Defines */
  25. #define V_OSCK 26000000 /* Clock output from T2 */
  26. #define V_SCLK (V_OSCK >> 1)
  27. #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
  28. #define CONFIG_SETUP_MEMORY_TAGS
  29. #define CONFIG_INITRD_TAG
  30. #define CONFIG_REVISION_TAG
  31. #define CONFIG_SERIAL_TAG
  32. /*
  33. * Size of malloc() pool
  34. */
  35. /* Sector */
  36. #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
  37. /*
  38. * Hardware drivers
  39. */
  40. /*
  41. * NS16550 Configuration
  42. */
  43. #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
  44. #define CONFIG_SYS_NS16550_SERIAL
  45. #define CONFIG_SYS_NS16550_REG_SIZE (-4)
  46. #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
  47. /*
  48. * select serial console configuration
  49. */
  50. #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
  51. /* allow to overwrite serial and ethaddr */
  52. #define CONFIG_ENV_OVERWRITE
  53. #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
  54. 115200}
  55. /* USB device configuration */
  56. #define CONFIG_USB_DEVICE
  57. #define CONFIG_USB_TTY
  58. /* commands to include */
  59. #define CONFIG_SYS_I2C
  60. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
  61. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  62. #define CONFIG_SYS_I2C_EEPROM_BUS 0
  63. #define CONFIG_I2C_MULTI_BUS
  64. /*
  65. * TWL4030
  66. */
  67. /*
  68. * Board NAND Info.
  69. */
  70. #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
  71. /* to access nand at */
  72. /* CS0 */
  73. #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
  74. /* devices */
  75. /* Environment information */
  76. #define CONFIG_EXTRA_ENV_SETTINGS \
  77. "loadaddr=0x82000000\0" \
  78. "usbtty=cdc_acm\0" \
  79. "console=ttyO2,115200n8\0" \
  80. "mpurate=500\0" \
  81. "vram=12M\0" \
  82. "dvimode=1024x768MR-16@60\0" \
  83. "defaultdisplay=dvi\0" \
  84. "mmcdev=0\0" \
  85. "mmcroot=/dev/mmcblk0p2 rw\0" \
  86. "mmcrootfstype=ext4 rootwait\0" \
  87. "nandroot=/dev/mtdblock4 rw\0" \
  88. "nandrootfstype=ubifs\0" \
  89. "mmcargs=setenv bootargs console=${console} " \
  90. "mpurate=${mpurate} " \
  91. "vram=${vram} " \
  92. "omapfb.mode=dvi:${dvimode} " \
  93. "omapdss.def_disp=${defaultdisplay} " \
  94. "root=${mmcroot} " \
  95. "rootfstype=${mmcrootfstype}\0" \
  96. "nandargs=setenv bootargs console=${console} " \
  97. "mpurate=${mpurate} " \
  98. "vram=${vram} " \
  99. "omapfb.mode=dvi:${dvimode} " \
  100. "omapdss.def_disp=${defaultdisplay} " \
  101. "root=${nandroot} " \
  102. "rootfstype=${nandrootfstype}\0" \
  103. "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
  104. "bootscript=echo Running bootscript from mmc ...; " \
  105. "source ${loadaddr}\0" \
  106. "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
  107. "mmcboot=echo Booting from mmc ...; " \
  108. "run mmcargs; " \
  109. "bootm ${loadaddr}\0" \
  110. "nandboot=echo Booting from nand ...; " \
  111. "run nandargs; " \
  112. "nand read ${loadaddr} 2a0000 400000; " \
  113. "bootm ${loadaddr}\0" \
  114. #define CONFIG_BOOTCOMMAND \
  115. "mmc dev ${mmcdev}; if mmc rescan; then " \
  116. "if run loadbootscript; then " \
  117. "run bootscript; " \
  118. "else " \
  119. "if run loaduimage; then " \
  120. "run mmcboot; " \
  121. "else run nandboot; " \
  122. "fi; " \
  123. "fi; " \
  124. "else run nandboot; fi"
  125. /*
  126. * Miscellaneous configurable options
  127. */
  128. #define CONFIG_TIMESTAMP
  129. #define CONFIG_SYS_AUTOLOAD "no"
  130. #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
  131. /* works on */
  132. #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
  133. 0x01F00000) /* 31MB */
  134. #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
  135. /* load address */
  136. /*
  137. * OMAP3 has 12 GP timers, they can be driven by the system clock
  138. * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
  139. * This rate is divided by a local divisor.
  140. */
  141. #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
  142. #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
  143. /*-----------------------------------------------------------------------
  144. * Physical Memory Map
  145. */
  146. #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
  147. /*-----------------------------------------------------------------------
  148. * FLASH and environment organization
  149. */
  150. /* **** PISMO SUPPORT *** */
  151. /* Monitor at start of flash */
  152. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  153. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
  154. /* additions for new relocation code, must be added to all boards */
  155. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  156. #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
  157. #define CONFIG_SYS_INIT_RAM_SIZE 0x800
  158. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
  159. CONFIG_SYS_INIT_RAM_SIZE - \
  160. GENERATED_GBL_DATA_SIZE)
  161. /* Status LED */
  162. #define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */
  163. #define CONFIG_SPLASHIMAGE_GUARD
  164. /* Display Configuration */
  165. #define LCD_BPP LCD_COLOR16
  166. #define CONFIG_SPLASH_SCREEN
  167. #define CONFIG_SPLASH_SOURCE
  168. #define CONFIG_BMP_16BPP
  169. #define CONFIG_SCF0403_LCD
  170. /* Defines for SPL */
  171. #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
  172. #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
  173. #define CONFIG_SPL_NAND_BASE
  174. #define CONFIG_SPL_NAND_DRIVERS
  175. #define CONFIG_SPL_NAND_ECC
  176. /* NAND boot config */
  177. #define CONFIG_SYS_NAND_5_ADDR_CYCLE
  178. #define CONFIG_SYS_NAND_PAGE_COUNT 64
  179. #define CONFIG_SYS_NAND_PAGE_SIZE 2048
  180. #define CONFIG_SYS_NAND_OOBSIZE 64
  181. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  182. #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
  183. /*
  184. * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
  185. * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
  186. */
  187. #define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \
  188. 10, 11, 12 }
  189. #define CONFIG_SYS_NAND_ECCSIZE 512
  190. #define CONFIG_SYS_NAND_ECCBYTES 3
  191. #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
  192. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
  193. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
  194. #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
  195. CONFIG_SPL_TEXT_BASE)
  196. /*
  197. * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
  198. * older x-loader implementations. And move the BSS area so that it
  199. * doesn't overlap with TEXT_BASE.
  200. */
  201. #define CONFIG_SPL_BSS_START_ADDR 0x80100000
  202. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
  203. #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
  204. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
  205. /* EEPROM */
  206. #define CONFIG_ENV_EEPROM_IS_ON_I2C
  207. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  208. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
  209. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  210. #define CONFIG_SYS_EEPROM_SIZE 256
  211. #endif /* __CONFIG_H */