ci20.h 2.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * CI20 configuration
  4. *
  5. * Copyright (c) 2013 Imagination Technologies
  6. * Author: Paul Burton <paul.burton@imgtec.com>
  7. */
  8. #ifndef __CONFIG_CI20_H__
  9. #define __CONFIG_CI20_H__
  10. #define CONFIG_SKIP_LOWLEVEL_INIT
  11. /* Ingenic JZ4780 clock configuration. */
  12. #define CONFIG_SYS_HZ 1000
  13. #define CONFIG_SYS_MHZ 1200
  14. #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
  15. /* Memory configuration */
  16. #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
  17. #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
  18. #define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
  19. #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */
  20. #define CONFIG_SYS_INIT_SP_OFFSET 0x400000
  21. #define CONFIG_SYS_LOAD_ADDR 0x81000000
  22. #define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
  23. #define CONFIG_SYS_MEMTEST_START 0x80000000
  24. #define CONFIG_SYS_MEMTEST_END 0x88000000
  25. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  26. /* NS16550-ish UARTs */
  27. #define CONFIG_SYS_NS16550_CLK 48000000
  28. #define CONFIG_SYS_CONSOLE_IS_IN_ENV
  29. /* Ethernet: davicom DM9000 */
  30. #define CONFIG_DRIVER_DM9000 1
  31. #define CONFIG_DM9000_BASE 0xb6000000
  32. #define DM9000_IO CONFIG_DM9000_BASE
  33. #define DM9000_DATA (CONFIG_DM9000_BASE + 2)
  34. /* Environment */
  35. #define CONFIG_SYS_MMC_ENV_DEV 0
  36. #define CONFIG_ENV_OVERWRITE
  37. /* Command line configuration. */
  38. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
  39. #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
  40. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  41. /* Boot argument buffer size */
  42. #define CONFIG_VERSION_VARIABLE /* U-BOOT version */
  43. /* Miscellaneous configuration options */
  44. #define CONFIG_SYS_BOOTM_LEN (64 << 20)
  45. /* SPL */
  46. #define CONFIG_SPL_STACK 0xf4008000 /* only max. 2KB spare! */
  47. #define CONFIG_SPL_MAX_SIZE ((14 * 1024) - 0xa00)
  48. #define CONFIG_SPL_BSS_START_ADDR 0xf4004000
  49. #define CONFIG_SPL_BSS_MAX_SIZE 0x00002000 /* 512KB, arbitrary */
  50. #define CONFIG_SPL_START_S_PATH "arch/mips/mach-jz47xx"
  51. #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x1c /* 14 KiB offset */
  52. #endif /* __CONFIG_CI20_H__ */