brppt1.h 6.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * brtpp1.h
  4. *
  5. * specific parts for B&R T-Series Motherboard
  6. *
  7. * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> -
  8. * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
  9. */
  10. #ifndef __CONFIG_BRPPT1_H__
  11. #define __CONFIG_BRPPT1_H__
  12. #include <configs/bur_cfg_common.h>
  13. #include <configs/bur_am335x_common.h>
  14. /* ------------------------------------------------------------------------- */
  15. /* memory */
  16. #define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024)
  17. #define CONFIG_SYS_BOOTM_LEN SZ_32M
  18. /* Clock Defines */
  19. #define V_OSCK 26000000 /* Clock output from T2 */
  20. #define V_SCLK (V_OSCK)
  21. #define CONFIG_POWER_TPS65217
  22. /* Support both device trees and ATAGs. */
  23. #define CONFIG_CMDLINE_TAG
  24. #define CONFIG_SETUP_MEMORY_TAGS
  25. #define CONFIG_INITRD_TAG
  26. /*#define CONFIG_MACH_TYPE 3589*/
  27. #define CONFIG_MACH_TYPE 0xFFFFFFFF /* TODO: check with kernel*/
  28. /*
  29. * When we have NAND flash we expect to be making use of mtdparts,
  30. * both for ease of use in U-Boot and for passing information on to
  31. * the Linux kernel.
  32. */
  33. #ifdef CONFIG_SPL_OS_BOOT
  34. #define CONFIG_SYS_SPL_ARGS_ADDR 0x80F80000
  35. /* RAW SD card / eMMC */
  36. #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */
  37. #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */
  38. #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */
  39. /* NAND */
  40. #ifdef CONFIG_MTD_RAW_NAND
  41. #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x140000
  42. #endif /* CONFIG_MTD_RAW_NAND */
  43. #endif /* CONFIG_SPL_OS_BOOT */
  44. #ifdef CONFIG_MTD_RAW_NAND
  45. #define CONFIG_SPL_NAND_BASE
  46. #define CONFIG_SPL_NAND_DRIVERS
  47. #define CONFIG_SPL_NAND_ECC
  48. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
  49. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
  50. #endif /* CONFIG_MTD_RAW_NAND */
  51. #ifdef CONFIG_MTD_RAW_NAND
  52. #define NANDTGTS \
  53. "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
  54. "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
  55. "cfgscr=mw ${dtbaddr} 0; nand read ${cfgaddr} cfgscr && source ${cfgaddr};" \
  56. " fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0" \
  57. "nandargs=setenv bootargs console=${console} ${optargs} ${optargs_rot} " \
  58. "root=mtd6 rootfstype=jffs2 b_mode=${b_mode}\0" \
  59. "b_nand=nand read ${loadaddr} kernel; nand read ${dtbaddr} dtb; " \
  60. "run nandargs; run cfgscr; bootz ${loadaddr} - ${dtbaddr}\0" \
  61. "b_tgts_std=usb0 nand net\0" \
  62. "b_tgts_rcy=net usb0 nand\0" \
  63. "b_tgts_pme=usb0 nand net\0"
  64. #else
  65. #define NANDTGTS ""
  66. #endif /* CONFIG_MTD_RAW_NAND */
  67. #define MMCSPI_TGTS \
  68. "t30args#0=setenv bootargs ${optargs_rot} ${optargs} console=${console} " \
  69. "b_mode=${b_mode} root=/dev/mmcblk0p2 rootfstype=ext4\0" \
  70. "b_t30lgcy#0=" \
  71. "load ${loaddev}:2 ${loadaddr} /boot/PPTImage.md5 && " \
  72. "load ${loaddev}:2 ${loadaddr} /boot/zImage && " \
  73. "load ${loaddev}:2 ${dtbaddr} /boot/am335x-ppt30.dtb || " \
  74. "load ${loaddev}:1 ${dtbaddr} am335x-ppt30-legacy.dtb; "\
  75. "run t30args#0; run cfgscr; bootz ${loadaddr} - ${dtbaddr}\0" \
  76. "t30args#1=setenv bootargs ${optargs_rot} ${optargs} console=${console} " \
  77. "b_mode=${b_mode}\0" \
  78. "b_t30lgcy#1=" \
  79. "load ${loaddev}:1 ${loadaddr} zImage && " \
  80. "load ${loaddev}:1 ${dtbaddr} am335x-ppt30.dtb && " \
  81. "load ${loaddev}:1 ${ramaddr} rootfsPPT30.uboot && " \
  82. "run t30args#1; run cfgscr; bootz ${loadaddr} ${ramaddr} ${dtbaddr}\0" \
  83. "b_mmc0=load ${loaddev}:1 ${scraddr} bootscr.img && source ${scraddr}\0" \
  84. "b_mmc1=load ${loaddev}:1 ${scraddr} /boot/bootscr.img && source ${scraddr}\0" \
  85. "b_tgts_std=mmc0 mmc1 t30lgcy#0 t30lgcy#1 usb0 net\0" \
  86. "b_tgts_rcy=t30lgcy#1 usb0 net\0" \
  87. "b_tgts_pme=net usb0 mmc0 mmc1\0" \
  88. "loaddev=mmc 1\0"
  89. #ifdef CONFIG_ENV_IS_IN_MMC
  90. #define MMCTGTS \
  91. MMCSPI_TGTS \
  92. "cfgscr=mw ${dtbaddr} 0;" \
  93. " mmc dev 1; mmc read ${cfgaddr} 200 80; source ${cfgaddr};" \
  94. " fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0"
  95. #else
  96. #define MMCTGTS ""
  97. #endif /* CONFIG_MMC */
  98. #ifdef CONFIG_SPI
  99. #define SPITGTS \
  100. MMCSPI_TGTS \
  101. "cfgscr=mw ${dtbaddr} 0;" \
  102. " sf probe; sf read ${cfgaddr} 0xC0000 10000; source ${cfgaddr};" \
  103. " fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0"
  104. #else
  105. #define SPITGTS ""
  106. #endif /* CONFIG_SPI */
  107. #define LOAD_OFFSET(x) 0x8##x
  108. #ifndef CONFIG_SPL_BUILD
  109. #define CONFIG_EXTRA_ENV_SETTINGS \
  110. BUR_COMMON_ENV \
  111. "verify=no\0" \
  112. "autoload=0\0" \
  113. "scraddr=" __stringify(LOAD_OFFSET(0000000)) "\0" \
  114. "cfgaddr=" __stringify(LOAD_OFFSET(0020000)) "\0" \
  115. "dtbaddr=" __stringify(LOAD_OFFSET(0040000)) "\0" \
  116. "loadaddr=" __stringify(LOAD_OFFSET(0100000)) "\0" \
  117. "ramaddr=" __stringify(LOAD_OFFSET(2000000)) "\0" \
  118. "console=ttyO0,115200n8\0" \
  119. "optargs=consoleblank=0 quiet panic=2\0" \
  120. "b_break=0\0" \
  121. "b_usb0=usb start && load usb 0 ${scraddr} bootscr.img && source ${scraddr}\0" \
  122. "b_net=tftp ${scraddr} netscript.img && source ${scraddr}\0" \
  123. MMCTGTS \
  124. SPITGTS \
  125. NANDTGTS \
  126. "b_deftgts=if test ${b_mode} = 12; then setenv b_tgts ${b_tgts_pme};" \
  127. " elif test ${b_mode} = 0; then setenv b_tgts ${b_tgts_rcy};" \
  128. " else setenv b_tgts ${b_tgts_std}; fi\0" \
  129. "b_default=run b_deftgts; for target in ${b_tgts};"\
  130. " do echo \"### booting ${target} ###\"; run b_${target};" \
  131. " if test ${b_break} = 1; then; exit; fi; done\0"
  132. #endif /* !CONFIG_SPL_BUILD*/
  133. #ifdef CONFIG_MTD_RAW_NAND
  134. /*
  135. * GPMC block. We support 1 device and the physical address to
  136. * access CS0 at is 0x8000000.
  137. */
  138. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  139. #define CONFIG_SYS_NAND_BASE 0x8000000
  140. /* don't change OMAP_ELM, ECCSCHEME. ROM code only supports this */
  141. #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
  142. #define CONFIG_SYS_NAND_5_ADDR_CYCLE
  143. #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
  144. #define CONFIG_SYS_NAND_PAGE_SIZE 2048
  145. #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
  146. CONFIG_SYS_NAND_PAGE_SIZE)
  147. #define CONFIG_SYS_NAND_OOBSIZE 64
  148. #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
  149. #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, \
  150. 10, 11, 12, 13, 14, 15, 16, 17, \
  151. 18, 19, 20, 21, 22, 23, 24, 25, \
  152. 26, 27, 28, 29, 30, 31, 32, 33, \
  153. 34, 35, 36, 37, 38, 39, 40, 41, \
  154. 42, 43, 44, 45, 46, 47, 48, 49, \
  155. 50, 51, 52, 53, 54, 55, 56, 57, }
  156. #define CONFIG_SYS_NAND_ECCSIZE 512
  157. #define CONFIG_SYS_NAND_ECCBYTES 14
  158. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
  159. #define CONFIG_NAND_OMAP_GPMC_WSCFG 1
  160. #endif /* CONFIG_MTD_RAW_NAND */
  161. #if defined(CONFIG_SPI)
  162. /* SPI Flash */
  163. /* Environment */
  164. #elif defined(CONFIG_ENV_IS_IN_MMC)
  165. #define CONFIG_SYS_MMC_ENV_DEV 1
  166. #define CONFIG_SYS_MMC_ENV_PART 2
  167. #elif defined(CONFIG_ENV_IS_IN_NAND)
  168. /* No NAND env support in SPL */
  169. #define CONFIG_SYS_ENV_SECT_SIZE CONFIG_ENV_SIZE
  170. #else
  171. #error "no storage for Environment defined!"
  172. #endif
  173. #endif /* ! __CONFIG_BRPPT1_H__ */