at91sam9263ek.h 7.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2007-2008
  4. * Stelian Pop <stelian@popies.net>
  5. * Lead Tech Design <www.leadtechdesign.com>
  6. *
  7. * Configuation settings for the AT91SAM9263EK board.
  8. */
  9. #ifndef __CONFIG_H
  10. #define __CONFIG_H
  11. /*
  12. * SoC must be defined first, before hardware.h is included.
  13. * In this case SoC is defined in boards.cfg.
  14. */
  15. #include <asm/hardware.h>
  16. /* ARM asynchronous clock */
  17. #define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
  18. #define CONFIG_SYS_AT91_SLOW_CLOCK 32768
  19. #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
  20. #define CONFIG_SETUP_MEMORY_TAGS 1
  21. #define CONFIG_INITRD_TAG 1
  22. #ifndef CONFIG_SYS_USE_BOOT_NORFLASH
  23. #define CONFIG_SKIP_LOWLEVEL_INIT
  24. #else
  25. #define CONFIG_SYS_USE_NORFLASH
  26. #endif
  27. /*
  28. * Hardware drivers
  29. */
  30. #define CONFIG_ATMEL_LEGACY
  31. /* LCD */
  32. #define LCD_BPP LCD_COLOR8
  33. #define CONFIG_LCD_LOGO 1
  34. #undef LCD_TEST_PATTERN
  35. #define CONFIG_LCD_INFO 1
  36. #define CONFIG_LCD_INFO_BELOW_LOGO 1
  37. #define CONFIG_ATMEL_LCD 1
  38. #define CONFIG_ATMEL_LCD_BGR555 1
  39. /*
  40. * BOOTP options
  41. */
  42. #define CONFIG_BOOTP_BOOTFILESIZE 1
  43. /* SDRAM */
  44. #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
  45. #define CONFIG_SYS_SDRAM_SIZE 0x04000000
  46. #define CONFIG_SYS_INIT_SP_ADDR \
  47. (ATMEL_BASE_SRAM1 + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
  48. /* NOR flash, if populated */
  49. #ifdef CONFIG_SYS_USE_NORFLASH
  50. #define PHYS_FLASH_1 0x10000000
  51. #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
  52. #define CONFIG_SYS_MAX_FLASH_SECT 256
  53. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  54. #define CONFIG_SYS_MONITOR_SEC 1:0-3
  55. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  56. #define CONFIG_SYS_MONITOR_LEN (256 << 10)
  57. /* Address and size of Primary Environment Sector */
  58. #define CONFIG_EXTRA_ENV_SETTINGS \
  59. "monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
  60. "update=" \
  61. "protect off ${monitor_base} +${filesize};" \
  62. "erase ${monitor_base} +${filesize};" \
  63. "cp.b ${fileaddr} ${monitor_base} ${filesize};" \
  64. "protect on ${monitor_base} +${filesize}\0"
  65. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  66. #define MASTER_PLL_MUL 171
  67. #define MASTER_PLL_DIV 14
  68. #define MASTER_PLL_OUT 3
  69. /* clocks */
  70. #define CONFIG_SYS_MOR_VAL \
  71. (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
  72. #define CONFIG_SYS_PLLAR_VAL \
  73. (AT91_PMC_PLLAR_29 | \
  74. AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \
  75. AT91_PMC_PLLXR_PLLCOUNT(63) | \
  76. AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \
  77. AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
  78. /* PCK/2 = MCK Master Clock from PLLA */
  79. #define CONFIG_SYS_MCKR1_VAL \
  80. (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \
  81. AT91_PMC_MCKR_MDIV_2)
  82. /* PCK/2 = MCK Master Clock from PLLA */
  83. #define CONFIG_SYS_MCKR2_VAL \
  84. (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \
  85. AT91_PMC_MCKR_MDIV_2)
  86. /* define PDC[31:16] as DATA[31:16] */
  87. #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
  88. /* no pull-up for D[31:16] */
  89. #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
  90. /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
  91. #define CONFIG_SYS_MATRIX_EBICSA_VAL \
  92. (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \
  93. AT91_MATRIX_CSA_EBI_CS1A)
  94. /* SDRAM */
  95. /* SDRAMC_MR Mode register */
  96. #define CONFIG_SYS_SDRC_MR_VAL1 0
  97. /* SDRAMC_TR - Refresh Timer register */
  98. #define CONFIG_SYS_SDRC_TR_VAL1 0x13C
  99. /* SDRAMC_CR - Configuration register*/
  100. #define CONFIG_SYS_SDRC_CR_VAL \
  101. (AT91_SDRAMC_NC_9 | \
  102. AT91_SDRAMC_NR_13 | \
  103. AT91_SDRAMC_NB_4 | \
  104. AT91_SDRAMC_CAS_3 | \
  105. AT91_SDRAMC_DBW_32 | \
  106. (1 << 8) | /* Write Recovery Delay */ \
  107. (7 << 12) | /* Row Cycle Delay */ \
  108. (2 << 16) | /* Row Precharge Delay */ \
  109. (2 << 20) | /* Row to Column Delay */ \
  110. (5 << 24) | /* Active to Precharge Delay */ \
  111. (1 << 28)) /* Exit Self Refresh to Active Delay */
  112. /* Memory Device Register -> SDRAM */
  113. #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
  114. #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
  115. #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
  116. #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
  117. #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
  118. #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
  119. #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
  120. #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
  121. #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
  122. #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
  123. #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
  124. #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
  125. #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
  126. #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
  127. #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
  128. #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
  129. #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
  130. #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
  131. /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
  132. #define CONFIG_SYS_SMC0_SETUP0_VAL \
  133. (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
  134. AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
  135. #define CONFIG_SYS_SMC0_PULSE0_VAL \
  136. (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
  137. AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
  138. #define CONFIG_SYS_SMC0_CYCLE0_VAL \
  139. (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
  140. #define CONFIG_SYS_SMC0_MODE0_VAL \
  141. (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
  142. AT91_SMC_MODE_DBW_16 | \
  143. AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
  144. /* user reset enable */
  145. #define CONFIG_SYS_RSTC_RMR_VAL \
  146. (AT91_RSTC_KEY | \
  147. AT91_RSTC_MR_URSTEN | \
  148. AT91_RSTC_MR_ERSTL(15))
  149. /* Disable Watchdog */
  150. #define CONFIG_SYS_WDTC_WDMR_VAL \
  151. (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
  152. AT91_WDT_MR_WDV(0xfff) | \
  153. AT91_WDT_MR_WDDIS | \
  154. AT91_WDT_MR_WDD(0xfff))
  155. #endif
  156. #endif
  157. /* NAND flash */
  158. #ifdef CONFIG_CMD_NAND
  159. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  160. #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
  161. #define CONFIG_SYS_NAND_DBW_8 1
  162. /* our ALE is AD21 */
  163. #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
  164. /* our CLE is AD22 */
  165. #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
  166. #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
  167. #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22
  168. #endif
  169. /* Ethernet */
  170. #define CONFIG_RESET_PHY_R 1
  171. #define CONFIG_AT91_WANTS_COMMON_PHY
  172. /* USB */
  173. #define CONFIG_USB_ATMEL
  174. #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
  175. #define CONFIG_USB_OHCI_NEW 1
  176. #define CONFIG_SYS_USB_OHCI_CPU_INIT 1
  177. #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
  178. #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
  179. #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
  180. #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
  181. #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
  182. #define CONFIG_SYS_MEMTEST_END 0x23e00000
  183. #ifdef CONFIG_SYS_USE_DATAFLASH
  184. /* bootstrap + u-boot + env + linux in dataflash on CS0 */
  185. #define CONFIG_BOOTCOMMAND "sf probe 0; " \
  186. "sf read 0x22000000 0x84000 0x294000; " \
  187. "bootm 0x22000000"
  188. #elif CONFIG_SYS_USE_NANDFLASH
  189. /* bootstrap + u-boot + env + linux in nandflash */
  190. #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm"
  191. #endif
  192. /*
  193. * Size of malloc() pool
  194. */
  195. #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
  196. #endif