at91rm9200ek.h 4.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2010 Andreas Bießmann <biessmann.devel@googlemail.com>
  4. *
  5. * based on previous work by
  6. *
  7. * Ulf Samuelsson <ulf@atmel.com>
  8. * Rick Bronson <rick@efn.org>
  9. *
  10. * Configuration settings for the AT91RM9200EK board.
  11. */
  12. #ifndef __AT91RM9200EK_CONFIG_H__
  13. #define __AT91RM9200EK_CONFIG_H__
  14. #include <linux/sizes.h>
  15. /*
  16. * set some initial configurations depending on configure target
  17. *
  18. * at91rm9200ek_config -> boot from 0x0 in NOR Flash at CS0
  19. * at91rm9200ek_ram_config -> continue booting from 0x20100000 in RAM; lowlevel
  20. * initialisation was done by some preloader
  21. */
  22. #ifdef CONFIG_RAMBOOT
  23. #define CONFIG_SKIP_LOWLEVEL_INIT
  24. #endif
  25. /*
  26. * AT91C_XTAL_CLOCK is the frequency of external xtal in hertz
  27. * AT91C_MAIN_CLOCK is the frequency of PLLA output
  28. * AT91C_MASTER_CLOCK is the peripherial clock
  29. * CONFIG_SYS_HZ_CLOCK is the value for CCR in tc0 (divider 2 is implicitely
  30. * set in arch/arm/cpu/arm920t/at91/timer.c)
  31. * CONFIG_SYS_HZ is the tick rate for timer tc0
  32. */
  33. #define AT91C_XTAL_CLOCK 18432000
  34. #define CONFIG_SYS_AT91_SLOW_CLOCK 32768
  35. #define AT91C_MAIN_CLOCK ((AT91C_XTAL_CLOCK / 4) * 39)
  36. #define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3 )
  37. #define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
  38. /* CPU configuration */
  39. #define CONFIG_AT91RM9200
  40. #define CONFIG_AT91RM9200EK
  41. #define USE_920T_MMU
  42. #include <asm/hardware.h> /* needed for port definitions */
  43. #define CONFIG_CMDLINE_TAG
  44. #define CONFIG_SETUP_MEMORY_TAGS
  45. #define CONFIG_INITRD_TAG
  46. /*
  47. * Memory Configuration
  48. */
  49. #define CONFIG_SYS_SDRAM_BASE 0x20000000
  50. #define CONFIG_SYS_SDRAM_SIZE SZ_32M
  51. #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
  52. #define CONFIG_SYS_MEMTEST_END \
  53. (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - SZ_256K)
  54. /*
  55. * LowLevel Init
  56. */
  57. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  58. #define CONFIG_SYS_USE_MAIN_OSCILLATOR
  59. /* flash */
  60. #define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
  61. #define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
  62. /* clocks */
  63. #define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
  64. #define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
  65. /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
  66. #define CONFIG_SYS_MCKR_VAL 0x00000202
  67. /* sdram */
  68. #define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
  69. #define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
  70. #define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
  71. #define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
  72. #define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */
  73. #define CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */
  74. #define CONFIG_SYS_SDRAM1 (CONFIG_SYS_SDRAM_BASE+0x80)
  75. #define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */
  76. #define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
  77. #define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
  78. #define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
  79. #define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
  80. #define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
  81. #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
  82. /*
  83. * Hardware drivers
  84. */
  85. /*
  86. * Choose a USART for serial console
  87. * CONFIG_DBGU is DBGU unit on J10
  88. * CONFIG_USART1 is USART1 on J14
  89. */
  90. #define CONFIG_ATMEL_USART
  91. #define CONFIG_USART_BASE ATMEL_BASE_DBGU
  92. #define CONFIG_USART_ID 0/* ignored in arm */
  93. /*
  94. * Command line configuration.
  95. */
  96. /*
  97. * Network Driver Setting
  98. */
  99. #define CONFIG_DRIVER_AT91EMAC
  100. #define CONFIG_SYS_RX_ETH_BUFFER 16
  101. #define CONFIG_RMII
  102. /*
  103. * NOR Flash
  104. */
  105. #define CONFIG_SYS_FLASH_BASE 0x10000000
  106. #define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE
  107. #define PHYS_FLASH_SIZE SZ_8M
  108. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  109. #define CONFIG_SYS_MAX_FLASH_SECT 256
  110. /*
  111. * USB Config
  112. */
  113. #define CONFIG_USB_ATMEL 1
  114. #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
  115. #define CONFIG_USB_OHCI_NEW 1
  116. #define CONFIG_SYS_USB_OHCI_CPU_INIT 1
  117. #define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_USB_HOST_BASE
  118. #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200"
  119. #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
  120. /*
  121. * Environment Settings
  122. */
  123. /*
  124. * after u-boot.bin
  125. */
  126. /* The following #defines are needed to get flash environment right */
  127. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  128. #define CONFIG_SYS_MONITOR_LEN SZ_256K
  129. /*
  130. * Boot option
  131. */
  132. /* default load address */
  133. #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_16M
  134. #define CONFIG_ENV_OVERWRITE
  135. /*
  136. * Shell Settings
  137. */
  138. /*
  139. * Size of malloc() pool
  140. */
  141. #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + SZ_128K, \
  142. SZ_4K)
  143. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \
  144. - GENERATED_GBL_DATA_SIZE)
  145. #endif /* __AT91RM9200EK_CONFIG_H__ */