apf27.h 7.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. *
  4. * Configuration settings for the Armadeus Project motherboard APF27
  5. *
  6. * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org>
  7. */
  8. #ifndef __CONFIG_H
  9. #define __CONFIG_H
  10. #define CONFIG_ENV_VERSION 10
  11. #define CONFIG_BOARD_NAME apf27
  12. /*
  13. * SoC configurations
  14. */
  15. #define CONFIG_MX27 /* This is a Freescale i.MX27 Chip */
  16. #define CONFIG_MACH_TYPE 1698 /* APF27 */
  17. /*
  18. * Enable the call to miscellaneous platform dependent initialization.
  19. */
  20. /*
  21. * SPL
  22. */
  23. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  24. #define CONFIG_SPL_MAX_SIZE 2048
  25. /* NAND boot config */
  26. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
  27. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800
  28. #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
  29. #define CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_MONITOR_LEN - 0x800
  30. /*
  31. * BOOTP options
  32. */
  33. #define CONFIG_BOOTP_BOOTFILESIZE
  34. #define CONFIG_BOOTP_DNS2
  35. #define CONFIG_HOSTNAME "apf27"
  36. #define CONFIG_ROOTPATH "/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root"
  37. /*
  38. * Memory configurations
  39. */
  40. #define CONFIG_NR_DRAM_POPULATED 1
  41. #define ACFG_SDRAM_MBYTE_SYZE 64
  42. #define PHYS_SDRAM_1 0xA0000000
  43. #define PHYS_SDRAM_2 0xB0000000
  44. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  45. #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (512<<10))
  46. #define CONFIG_SYS_MEMTEST_START 0xA0000000 /* memtest test area */
  47. #define CONFIG_SYS_MEMTEST_END 0xA0300000 /* 3 MiB RAM test */
  48. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE \
  49. + PHYS_SDRAM_1_SIZE - 0x0100000)
  50. /*
  51. * FLASH organization
  52. */
  53. #define ACFG_MONITOR_OFFSET 0x00000000
  54. #define CONFIG_SYS_MONITOR_LEN 0x00100000 /* 1MiB */
  55. #define CONFIG_ENV_OVERWRITE
  56. #define CONFIG_ENV_RANGE 0X00080000 /* 512kB */
  57. #define CONFIG_FIRMWARE_OFFSET 0x00200000
  58. #define CONFIG_FIRMWARE_SIZE 0x00080000 /* 512kB */
  59. #define CONFIG_KERNEL_OFFSET 0x00300000
  60. #define CONFIG_ROOTFS_OFFSET 0x00800000
  61. /*
  62. * U-Boot general configurations
  63. */
  64. #define CONFIG_SYS_CBSIZE 2048 /* console I/O buffer */
  65. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  66. /* Boot argument buffer size */
  67. /*
  68. * Boot Linux
  69. */
  70. #define CONFIG_CMDLINE_TAG /* send commandline to Kernel */
  71. #define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */
  72. #define CONFIG_INITRD_TAG /* send initrd params */
  73. #define CONFIG_BOOTFILE __stringify(CONFIG_BOARD_NAME) "-linux.bin"
  74. #define ACFG_CONSOLE_DEV ttySMX0
  75. #define CONFIG_BOOTCOMMAND "run ubifsboot"
  76. #define CONFIG_SYS_AUTOLOAD "no"
  77. /*
  78. * Default load address for user programs and kernel
  79. */
  80. #define CONFIG_LOADADDR 0xA0000000
  81. #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
  82. /*
  83. * Extra Environments
  84. */
  85. #define CONFIG_EXTRA_ENV_SETTINGS \
  86. "env_version=" __stringify(CONFIG_ENV_VERSION) "\0" \
  87. "consoledev=" __stringify(ACFG_CONSOLE_DEV) "\0" \
  88. "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
  89. "partition=nand0,6\0" \
  90. "u-boot_addr=" __stringify(ACFG_MONITOR_OFFSET) "\0" \
  91. "env_addr=" __stringify(CONFIG_ENV_OFFSET) "\0" \
  92. "firmware_addr=" __stringify(CONFIG_FIRMWARE_OFFSET) "\0" \
  93. "firmware_size=" __stringify(CONFIG_FIRMWARE_SIZE) "\0" \
  94. "kernel_addr=" __stringify(CONFIG_KERNEL_OFFSET) "\0" \
  95. "rootfs_addr=" __stringify(CONFIG_ROOTFS_OFFSET) "\0" \
  96. "board_name=" __stringify(CONFIG_BOARD_NAME) "\0" \
  97. "kernel_addr_r=A0000000\0" \
  98. "check_env=if test -n ${flash_env_version}; " \
  99. "then env default env_version; " \
  100. "else env set flash_env_version ${env_version}; env save; "\
  101. "fi; " \
  102. "if itest ${flash_env_version} < ${env_version}; then " \
  103. "echo \"*** Warning - Environment version" \
  104. " change suggests: run flash_reset_env; reset\"; "\
  105. "env default flash_reset_env; "\
  106. "fi; \0" \
  107. "check_flash=nand lock; nand unlock ${env_addr}; \0" \
  108. "flash_reset_env=env default -f -a; saveenv; run update_env;" \
  109. "echo Flash environment variables erased!\0" \
  110. "download_uboot=tftpboot ${loadaddr} ${board_name}" \
  111. "-u-boot-with-spl.bin\0" \
  112. "flash_uboot=nand unlock ${u-boot_addr} ;" \
  113. "nand erase.part u-boot;" \
  114. "if nand write.trimffs ${fileaddr} ${u-boot_addr} ${filesize};"\
  115. "then nand lock; nand unlock ${env_addr};" \
  116. "echo Flashing of uboot succeed;" \
  117. "else echo Flashing of uboot failed;" \
  118. "fi; \0" \
  119. "update_uboot=run download_uboot flash_uboot\0" \
  120. "download_env=tftpboot ${loadaddr} ${board_name}" \
  121. "-u-boot-env.txt\0" \
  122. "flash_env=env import -t ${loadaddr}; env save; \0" \
  123. "update_env=run download_env flash_env\0" \
  124. "update_all=run update_env update_uboot\0" \
  125. "unlock_regs=mw 10000008 0; mw 10020008 0\0" \
  126. /*
  127. * Serial Driver
  128. */
  129. #define CONFIG_MXC_UART
  130. #define CONFIG_MXC_UART_BASE UART1_BASE
  131. /*
  132. * NOR
  133. */
  134. /*
  135. * NAND
  136. */
  137. #define CONFIG_MXC_NAND_REGS_BASE 0xD8000000
  138. #define CONFIG_SYS_NAND_BASE CONFIG_MXC_NAND_REGS_BASE
  139. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  140. #define CONFIG_MXC_NAND_HWECC
  141. #define CONFIG_SYS_NAND_LARGEPAGE
  142. #define CONFIG_SYS_NAND_PAGE_SIZE 2048
  143. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  144. #define CONFIG_SYS_NAND_PAGE_COUNT CONFIG_SYS_NAND_BLOCK_SIZE / \
  145. CONFIG_SYS_NAND_PAGE_SIZE
  146. #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
  147. #define CONFIG_SYS_NAND_BAD_BLOCK_POS 11
  148. #define NAND_MAX_CHIPS 1
  149. #define CONFIG_FLASH_SHOW_PROGRESS 45
  150. #define CONFIG_SYS_NAND_QUIET 1
  151. /*
  152. * Partitions & Filsystems
  153. */
  154. /*
  155. * Ethernet (on SOC imx FEC)
  156. */
  157. #define CONFIG_FEC_MXC
  158. #define CONFIG_FEC_MXC_PHYADDR 0x1f
  159. /*
  160. * FPGA
  161. */
  162. #define CONFIG_FPGA_COUNT 1
  163. #define CONFIG_SYS_FPGA_WAIT 250 /* 250 ms */
  164. #define CONFIG_SYS_FPGA_PROG_FEEDBACK
  165. #define CONFIG_SYS_FPGA_CHECK_CTRLC
  166. #define CONFIG_SYS_FPGA_CHECK_ERROR
  167. /*
  168. * Fuses - IIM
  169. */
  170. #ifdef CONFIG_CMD_IMX_FUSE
  171. #define IIM_MAC_BANK 0
  172. #define IIM_MAC_ROW 5
  173. #define IIM0_SCC_KEY 11
  174. #define IIM1_SUID 1
  175. #endif
  176. /*
  177. * I2C
  178. */
  179. #ifdef CONFIG_CMD_I2C
  180. #define CONFIG_SYS_I2C
  181. #define CONFIG_SYS_I2C_MXC
  182. #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
  183. #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
  184. #define CONFIG_SYS_MXC_I2C1_SPEED 100000 /* 100 kHz */
  185. #define CONFIG_SYS_MXC_I2C1_SLAVE 0x7F
  186. #define CONFIG_SYS_MXC_I2C2_SPEED 100000 /* 100 kHz */
  187. #define CONFIG_SYS_MXC_I2C2_SLAVE 0x7F
  188. #define CONFIG_SYS_I2C_NOPROBES { }
  189. #ifdef CONFIG_CMD_EEPROM
  190. # define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24LC02 */
  191. # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
  192. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  193. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* msec */
  194. #endif /* CONFIG_CMD_EEPROM */
  195. #endif /* CONFIG_CMD_I2C */
  196. /*
  197. * SD/MMC
  198. */
  199. #ifdef CONFIG_CMD_MMC
  200. #define CONFIG_MXC_MCI_REGS_BASE 0x10014000
  201. #endif
  202. /*
  203. * RTC
  204. */
  205. #ifdef CONFIG_CMD_DATE
  206. #define CONFIG_RTC_DS1374
  207. #define CONFIG_SYS_RTC_BUS_NUM 0
  208. #endif /* CONFIG_CMD_DATE */
  209. /*
  210. * PLL
  211. *
  212. * 31 | x |x| x x x x |x x x x x x x x x x |x x|x x x x|x x x x x x x x x x| 0
  213. * |CPLM|X|----PD---|--------MFD---------|XXX|--MFI--|-----MFN-----------|
  214. */
  215. #define CONFIG_MX27_CLK32 32768 /* 32768 or 32000 Hz crystal */
  216. #if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
  217. /* micron 64MB */
  218. #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
  219. #define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */
  220. #endif
  221. #if (ACFG_SDRAM_MBYTE_SYZE == 128)
  222. /* micron 128MB */
  223. #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
  224. #define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */
  225. #endif
  226. #if (ACFG_SDRAM_MBYTE_SYZE == 256)
  227. /* micron 256MB */
  228. #define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */
  229. #define PHYS_SDRAM_2_SIZE 0x10000000 /* 256 MB */
  230. #endif
  231. #endif /* __CONFIG_H */