anole-c810.h 3.6 KB

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  1. /*
  2. * Copyright (C) 2017-2020 Alibaba Group Holding Limited
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #ifndef __CONFIG_H
  7. #define __CONFIG_H
  8. #include <linux/sizes.h>
  9. // #define DEBUG
  10. #define SPL_SSEG0_BASEADDRESS 0x40000000
  11. #define SSEG0_BASEADDRESS 0x40000000
  12. #define SSEG1_BASEADDRESS 0xe0000000
  13. #define CONFIG_NR_DRAM_BANKS 1
  14. #define CONFIG_BOARD_EARLY_INIT_R
  15. #define CONFIG_BOARD_EARLY_INIT_F
  16. #define CONFIG_SYS_HZ 1000
  17. /*
  18. * LSP : Timer UART
  19. * HSP : SPI0 EMMC
  20. */
  21. #ifdef CONFIG_IS_ASIC
  22. #define CPU_DEFAULT_FREQ 1000000000
  23. #define HSP_DEFAULT_FREQ 250000000
  24. #define LSP_DEFAULT_FREQ 62500000
  25. #else
  26. #define CPU_DEFAULT_FREQ 50000000
  27. #define HSP_DEFAULT_FREQ 50000000
  28. #define LSP_DEFAULT_FREQ 50000000
  29. #endif
  30. #define LSP_CLOCK (LSP_DEFAULT_FREQ / 1000000)
  31. #define CONFIG_SYS_CLK_FREQ CPU_DEFAULT_FREQ
  32. /* Physical Memory Map */
  33. #define PHYS_SRAM_1 0xfe400000
  34. #define PHYS_SDRAM_1 0x40000000
  35. #define PHYS_SDRAM_1_SIZE 0x18000000 /* 384M */
  36. #define CONFIG_SYS_TEXT_BASE 0x57800000
  37. #define CONFIG_SYS_LOAD_ADDR 0x80000000
  38. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x80000 - 0x8)
  39. #define CONFIG_SYS_MALLOC_LEN SZ_2M
  40. #define CONFIG_SYS_BOOTM_LEN SZ_32M
  41. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  42. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  43. #define CONFIG_SPL_STACK (PHYS_SRAM_1 + 0x8000 - 0x8)
  44. #define CONFIG_SPL_MAX_FOOTPRINT 0x4000
  45. #ifdef CONFIG_SPL_BUILD
  46. #define INTC_BASEADDRESS 0xfe3f0000
  47. #define TIMER_BASEADDRESS 0xfff70000
  48. #define ERAGON_MMC0_BASE 0xfffb0000
  49. #else
  50. #define INTC_BASEADDRESS 0xbe3f0000
  51. #define TIMER_BASEADDRESS 0xbff70000
  52. #define ERAGON_MMC0_BASE 0xbffb0000
  53. #endif
  54. #define UBOOT_INTERNAL_VERSION "0.3"
  55. #define CONFIG_C810_CSKY
  56. #define CONFIG_BOARD_PRINTF_SUPPORT
  57. #define CONFIG_BOARD_CONSOLE_SUPPORT
  58. #define CONFIG_BOARD_MMC_SUPPORT
  59. #define CONFIG_BOARD_SPIFLASH_SUPPORT
  60. #define CONFIG_SUPPORT_EMMC_BOOT
  61. #define HAVE_BLOCK_DEVICE
  62. #define TIMER_ID 0
  63. #define TIME_IRQ 4
  64. #define CONFIG_BAUDRATE 115200
  65. #define TIMEOUT_COUNT_TIMER TIMER0
  66. #define TIMEOUT_VALUE 500
  67. #define CONFIG_SYS_CBSIZE 256 /* This is Console Buffer size */
  68. #define CONFIG_SYS_MAXARGS 16
  69. /* NAND configuration */
  70. #ifdef CONFIG_CMD_NAND
  71. #define CONFIG_NAND_ERAGON 1
  72. #define CONFIG_SYS_ERAGON_NAND_HWECC
  73. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  74. #define CONFIG_SYS_NAND_BASE 0x4e000000
  75. #endif
  76. /* Network Configuration */
  77. #define CONFIG_DW_ALTDESCRIPTOR
  78. #define CONFIG_MII 1
  79. #define CONFIG_PHY_MARVELL 1
  80. #define CONFIG_NET_RETRY_COUNT 20
  81. #define PHYS_FLASH_1 0x00200000 /* Flash Bank #0 */
  82. #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
  83. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  84. #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x070000)
  85. #define CONFIG_SYS_MMC_ENV_DEV 0
  86. /* Image address in Flash */
  87. #define FLASH_SPL_READ_ADDR 0x100000 /* 1M */
  88. #define FLASH_SPL_SIZE 0x010000 /* 64K */
  89. #define FLASH_FDT_READ_ADDR 0x130000 /* 1M+192K */
  90. #define FLASH_FDT_SIZE 0x010000
  91. #define FLASH_UBOOT_READ_ADDR 0x140000 /* 1M+256K */
  92. #define FLASH_UBOOT_SIZE 0x080000
  93. /* Environment options */
  94. #define CONFIG_EXTRA_ENV_SETTINGS \
  95. "dtb_load_addr_virt=0x8f000000\0" \
  96. "dtb_load_addr_phys=0x4f000000\0" \
  97. "linux_load_addr_virt=0x90000000\0" \
  98. "linux_load_addr_phys=0x50000000\0"
  99. #undef CONFIG_BOOTCOMMAND
  100. #define CONFIG_BOOTCOMMAND \
  101. "bootm ${linux_load_addr_virt} "
  102. #endif /* __CONFIG_H */