adp-ag101p.h 8.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2011 Andes Technology Corporation
  4. * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
  5. * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
  6. */
  7. #ifndef __CONFIG_H
  8. #define __CONFIG_H
  9. #include <asm/arch-ag101/ag101.h>
  10. /*
  11. * CPU and Board Configuration Options
  12. */
  13. #define CONFIG_USE_INTERRUPT
  14. #define CONFIG_SKIP_LOWLEVEL_INIT
  15. #define CONFIG_ARCH_MAP_SYSMEM
  16. #define CONFIG_BOOTP_SEND_HOSTNAME
  17. #define CONFIG_BOOTP_SERVERIP
  18. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  19. #define CONFIG_MEM_REMAP
  20. #endif
  21. #ifdef CONFIG_SKIP_LOWLEVEL_INIT
  22. #ifdef CONFIG_OF_CONTROL
  23. #undef CONFIG_OF_SEPARATE
  24. #define CONFIG_OF_EMBED
  25. #endif
  26. #endif
  27. /*
  28. * Timer
  29. */
  30. #define CONFIG_SYS_CLK_FREQ 39062500
  31. #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
  32. /*
  33. * Use Externel CLOCK or PCLK
  34. */
  35. #undef CONFIG_FTRTC010_EXTCLK
  36. #ifndef CONFIG_FTRTC010_EXTCLK
  37. #define CONFIG_FTRTC010_PCLK
  38. #endif
  39. #ifdef CONFIG_FTRTC010_EXTCLK
  40. #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */
  41. #else
  42. #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */
  43. #endif
  44. #define TIMER_LOAD_VAL 0xffffffff
  45. /*
  46. * Real Time Clock
  47. */
  48. #define CONFIG_RTC_FTRTC010
  49. /*
  50. * Real Time Clock Divider
  51. * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
  52. */
  53. #define OSC_5MHZ (5*1000000)
  54. #define OSC_CLK (4*OSC_5MHZ)
  55. #define RTC_DIV_COUNT (0.5) /* Why?? */
  56. /*
  57. * Serial console configuration
  58. */
  59. /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
  60. #define CONFIG_SYS_NS16550_SERIAL
  61. #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
  62. #ifndef CONFIG_DM_SERIAL
  63. #define CONFIG_SYS_NS16550_REG_SIZE -4
  64. #endif
  65. #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */
  66. /*
  67. * Miscellaneous configurable options
  68. */
  69. /*
  70. * Size of malloc() pool
  71. */
  72. /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
  73. #define CONFIG_SYS_MALLOC_LEN (512 << 10)
  74. /*
  75. * AHB Controller configuration
  76. */
  77. #define CONFIG_FTAHBC020S
  78. #ifdef CONFIG_FTAHBC020S
  79. #include <faraday/ftahbc020s.h>
  80. /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
  81. #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100
  82. /*
  83. * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
  84. * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
  85. * in C language.
  86. */
  87. #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
  88. (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
  89. FTAHBC020S_SLAVE_BSR_SIZE(0xb))
  90. #endif
  91. /*
  92. * Watchdog
  93. */
  94. #define CONFIG_FTWDT010_WATCHDOG
  95. /*
  96. * PMU Power controller configuration
  97. */
  98. #define CONFIG_PMU
  99. #define CONFIG_FTPMU010_POWER
  100. #ifdef CONFIG_FTPMU010_POWER
  101. #include <faraday/ftpmu010.h>
  102. #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E
  103. #define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \
  104. FTPMU010_SDRAMHTC_EBIDATA_DCSR | \
  105. FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \
  106. FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
  107. FTPMU010_SDRAMHTC_CKE_DCSR | \
  108. FTPMU010_SDRAMHTC_DQM_DCSR | \
  109. FTPMU010_SDRAMHTC_SDCLK_DCSR)
  110. #endif
  111. /*
  112. * SDRAM controller configuration
  113. */
  114. #define CONFIG_FTSDMC021
  115. #ifdef CONFIG_FTSDMC021
  116. #include <faraday/ftsdmc021.h>
  117. #define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \
  118. FTSDMC021_TP1_TRP(1) | \
  119. FTSDMC021_TP1_TRCD(1) | \
  120. FTSDMC021_TP1_TRF(3) | \
  121. FTSDMC021_TP1_TWR(1) | \
  122. FTSDMC021_TP1_TCL(2))
  123. #define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \
  124. FTSDMC021_TP2_INI_REFT(8) | \
  125. FTSDMC021_TP2_REF_INTV(0x180))
  126. /*
  127. * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
  128. * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
  129. * C language.
  130. */
  131. #define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \
  132. FTSDMC021_CR1_DSZ(3) | \
  133. FTSDMC021_CR1_MBW(2) | \
  134. FTSDMC021_CR1_BNKSIZE(6))
  135. #define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \
  136. FTSDMC021_CR2_IREF | \
  137. FTSDMC021_CR2_ISMR)
  138. #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
  139. #define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \
  140. CONFIG_SYS_FTSDMC021_BANK0_BASE)
  141. #define CONFIG_SYS_FTSDMC021_BANK1_BASE \
  142. (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20))
  143. #define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \
  144. CONFIG_SYS_FTSDMC021_BANK1_BASE)
  145. #endif
  146. /*
  147. * Physical Memory Map
  148. */
  149. #ifdef CONFIG_SKIP_LOWLEVEL_INIT
  150. #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
  151. #else
  152. #ifdef CONFIG_MEM_REMAP
  153. #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
  154. #else
  155. #define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */
  156. #endif
  157. #endif
  158. #define PHYS_SDRAM_1 \
  159. (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
  160. #ifdef CONFIG_SKIP_LOWLEVEL_INIT
  161. #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
  162. #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
  163. #else
  164. #ifdef CONFIG_MEM_REMAP
  165. #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
  166. #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
  167. #else
  168. #define PHYS_SDRAM_0_SIZE 0x08000000 /* 128 MB */
  169. #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
  170. #endif
  171. #endif
  172. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
  173. #ifdef CONFIG_MEM_REMAP
  174. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
  175. GENERATED_GBL_DATA_SIZE)
  176. #else
  177. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
  178. GENERATED_GBL_DATA_SIZE)
  179. #endif /* CONFIG_MEM_REMAP */
  180. /*
  181. * Load address and memory test area should agree with
  182. * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself.
  183. */
  184. #define CONFIG_SYS_LOAD_ADDR 0x300000
  185. /* memtest works on 63 MB in DRAM */
  186. #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
  187. #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000)
  188. /*
  189. * Static memory controller configuration
  190. */
  191. #define CONFIG_FTSMC020
  192. #ifdef CONFIG_FTSMC020
  193. #include <faraday/ftsmc020.h>
  194. #define CONFIG_SYS_FTSMC020_CONFIGS { \
  195. { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
  196. { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
  197. }
  198. #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */
  199. #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \
  200. FTSMC020_BANK_SIZE_32M | \
  201. FTSMC020_BANK_MBW_32)
  202. #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \
  203. FTSMC020_TPR_AST(1) | \
  204. FTSMC020_TPR_CTW(1) | \
  205. FTSMC020_TPR_ATI(1) | \
  206. FTSMC020_TPR_AT2(1) | \
  207. FTSMC020_TPR_WTC(1) | \
  208. FTSMC020_TPR_AHT(1) | \
  209. FTSMC020_TPR_TRNA(1))
  210. #endif
  211. /*
  212. * FLASH on ADP_AG101P is connected to BANK0
  213. * Just disalbe the other BANK to avoid detection error.
  214. */
  215. #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
  216. FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
  217. FTSMC020_BANK_SIZE_32M | \
  218. FTSMC020_BANK_MBW_32)
  219. #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \
  220. FTSMC020_TPR_CTW(3) | \
  221. FTSMC020_TPR_ATI(0xf) | \
  222. FTSMC020_TPR_AT2(3) | \
  223. FTSMC020_TPR_WTC(3) | \
  224. FTSMC020_TPR_AHT(3) | \
  225. FTSMC020_TPR_TRNA(0xf))
  226. #define FTSMC020_BANK1_CONFIG (0x00)
  227. #define FTSMC020_BANK1_TIMING (0x00)
  228. #endif /* CONFIG_FTSMC020 */
  229. /*
  230. * FLASH and environment organization
  231. */
  232. /* use CFI framework */
  233. #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  234. #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
  235. /* support JEDEC */
  236. /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
  237. #ifdef CONFIG_SKIP_LOWLEVEL_INIT
  238. #define PHYS_FLASH_1 0x80000000 /* BANK 0 */
  239. #else
  240. #ifdef CONFIG_MEM_REMAP
  241. #define PHYS_FLASH_1 0x80000000 /* BANK 0 */
  242. #else
  243. #define PHYS_FLASH_1 0x00000000 /* BANK 0 */
  244. #endif
  245. #endif /* CONFIG_MEM_REMAP */
  246. #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
  247. #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
  248. #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
  249. #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
  250. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
  251. /* max number of memory banks */
  252. /*
  253. * There are 4 banks supported for this Controller,
  254. * but we have only 1 bank connected to flash on board
  255. */
  256. #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
  257. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  258. #endif
  259. #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
  260. /* max number of sectors on one chip */
  261. #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
  262. #define CONFIG_SYS_MAX_FLASH_SECT 512
  263. /* environments */
  264. #define CONFIG_ENV_OVERWRITE
  265. /*
  266. * For booting Linux, the board info and command line data
  267. * have to be in the first 16 MB of memory, since this is
  268. * the maximum mapped by the Linux kernel during initialization.
  269. */
  270. /* Initial Memory map for Linux*/
  271. #define CONFIG_SYS_BOOTMAPSZ (64 << 20)
  272. /* Increase max gunzip size */
  273. #define CONFIG_SYS_BOOTM_LEN (64 << 20)
  274. #endif /* __CONFIG_H */