adp-ae3xx.h 5.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2011 Andes Technology Corporation
  4. * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
  5. * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
  6. */
  7. #ifndef __CONFIG_H
  8. #define __CONFIG_H
  9. #include <asm/arch-ae3xx/ae3xx.h>
  10. /*
  11. * CPU and Board Configuration Options
  12. */
  13. #define CONFIG_USE_INTERRUPT
  14. #define CONFIG_SKIP_LOWLEVEL_INIT
  15. #define CONFIG_SKIP_TRUNOFF_WATCHDOG
  16. #define CONFIG_ARCH_MAP_SYSMEM
  17. #define CONFIG_BOOTP_SEND_HOSTNAME
  18. #define CONFIG_BOOTP_SERVERIP
  19. #ifdef CONFIG_SKIP_LOWLEVEL_INIT
  20. #ifdef CONFIG_OF_CONTROL
  21. #undef CONFIG_OF_SEPARATE
  22. #define CONFIG_OF_EMBED
  23. #endif
  24. #endif
  25. /*
  26. * Timer
  27. */
  28. #define CONFIG_SYS_CLK_FREQ 39062500
  29. #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
  30. /*
  31. * Use Externel CLOCK or PCLK
  32. */
  33. #undef CONFIG_FTRTC010_EXTCLK
  34. #ifndef CONFIG_FTRTC010_EXTCLK
  35. #define CONFIG_FTRTC010_PCLK
  36. #endif
  37. #ifdef CONFIG_FTRTC010_EXTCLK
  38. #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */
  39. #else
  40. #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */
  41. #endif
  42. #define TIMER_LOAD_VAL 0xffffffff
  43. /*
  44. * Real Time Clock
  45. */
  46. #define CONFIG_RTC_FTRTC010
  47. /*
  48. * Real Time Clock Divider
  49. * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
  50. */
  51. #define OSC_5MHZ (5*1000000)
  52. #define OSC_CLK (4*OSC_5MHZ)
  53. #define RTC_DIV_COUNT (0.5) /* Why?? */
  54. /*
  55. * Serial console configuration
  56. */
  57. /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
  58. #define CONFIG_SYS_NS16550_SERIAL
  59. #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
  60. #ifndef CONFIG_DM_SERIAL
  61. #define CONFIG_SYS_NS16550_REG_SIZE -4
  62. #endif
  63. #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */
  64. /*
  65. * Miscellaneous configurable options
  66. */
  67. /*
  68. * Size of malloc() pool
  69. */
  70. /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
  71. #define CONFIG_SYS_MALLOC_LEN (512 << 10)
  72. /*
  73. * Physical Memory Map
  74. */
  75. #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
  76. #define PHYS_SDRAM_1 \
  77. (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
  78. #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
  79. #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
  80. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
  81. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
  82. GENERATED_GBL_DATA_SIZE)
  83. /*
  84. * Load address and memory test area should agree with
  85. * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself.
  86. */
  87. #define CONFIG_SYS_LOAD_ADDR 0x300000
  88. /* memtest works on 63 MB in DRAM */
  89. #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
  90. #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000)
  91. /*
  92. * Static memory controller configuration
  93. */
  94. #define CONFIG_FTSMC020
  95. #ifdef CONFIG_FTSMC020
  96. #include <faraday/ftsmc020.h>
  97. #define CONFIG_SYS_FTSMC020_CONFIGS { \
  98. { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
  99. { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
  100. }
  101. #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */
  102. #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \
  103. FTSMC020_BANK_SIZE_32M | \
  104. FTSMC020_BANK_MBW_32)
  105. #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \
  106. FTSMC020_TPR_AST(1) | \
  107. FTSMC020_TPR_CTW(1) | \
  108. FTSMC020_TPR_ATI(1) | \
  109. FTSMC020_TPR_AT2(1) | \
  110. FTSMC020_TPR_WTC(1) | \
  111. FTSMC020_TPR_AHT(1) | \
  112. FTSMC020_TPR_TRNA(1))
  113. #endif
  114. /*
  115. * FLASH on ADP_AG101P is connected to BANK0
  116. * Just disalbe the other BANK to avoid detection error.
  117. */
  118. #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
  119. FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
  120. FTSMC020_BANK_SIZE_32M | \
  121. FTSMC020_BANK_MBW_32)
  122. #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \
  123. FTSMC020_TPR_CTW(3) | \
  124. FTSMC020_TPR_ATI(0xf) | \
  125. FTSMC020_TPR_AT2(3) | \
  126. FTSMC020_TPR_WTC(3) | \
  127. FTSMC020_TPR_AHT(3) | \
  128. FTSMC020_TPR_TRNA(0xf))
  129. #define FTSMC020_BANK1_CONFIG (0x00)
  130. #define FTSMC020_BANK1_TIMING (0x00)
  131. #endif /* CONFIG_FTSMC020 */
  132. /*
  133. * FLASH and environment organization
  134. */
  135. /* use CFI framework */
  136. #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  137. #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
  138. /* support JEDEC */
  139. #ifdef CONFIG_CFI_FLASH
  140. #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
  141. #endif
  142. /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
  143. #define PHYS_FLASH_1 0x88000000 /* BANK 0 */
  144. #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
  145. #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
  146. #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
  147. #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
  148. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
  149. /* max number of memory banks */
  150. /*
  151. * There are 4 banks supported for this Controller,
  152. * but we have only 1 bank connected to flash on board
  153. */
  154. #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
  155. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  156. #endif
  157. #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
  158. /* max number of sectors on one chip */
  159. #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
  160. #define CONFIG_SYS_MAX_FLASH_SECT 512
  161. /* environments */
  162. #define CONFIG_ENV_OVERWRITE
  163. /* SPI FLASH */
  164. /*
  165. * For booting Linux, the board info and command line data
  166. * have to be in the first 16 MB of memory, since this is
  167. * the maximum mapped by the Linux kernel during initialization.
  168. */
  169. /* Initial Memory map for Linux*/
  170. #define CONFIG_SYS_BOOTMAPSZ (64 << 20)
  171. /* Increase max gunzip size */
  172. #define CONFIG_SYS_BOOTM_LEN (64 << 20)
  173. #endif /* __CONFIG_H */