T4240RDB.h 22 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. */
  5. /*
  6. * T4240 RDB board configuration file
  7. */
  8. #ifndef __CONFIG_H
  9. #define __CONFIG_H
  10. #define CONFIG_FSL_SATA_V2
  11. #define CONFIG_PCIE4
  12. #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
  13. #ifdef CONFIG_RAMBOOT_PBL
  14. #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
  15. #ifndef CONFIG_SDCARD
  16. #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
  17. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  18. #else
  19. #define CONFIG_SPL_FLUSH_IMAGE
  20. #define CONFIG_SPL_PAD_TO 0x40000
  21. #define CONFIG_SPL_MAX_SIZE 0x28000
  22. #define RESET_VECTOR_OFFSET 0x27FFC
  23. #define BOOT_PAGE_OFFSET 0x27000
  24. #ifdef CONFIG_SDCARD
  25. #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
  26. #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
  27. #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
  28. #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
  29. #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
  30. #ifndef CONFIG_SPL_BUILD
  31. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  32. #endif
  33. #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg
  34. #endif
  35. #ifdef CONFIG_SPL_BUILD
  36. #define CONFIG_SPL_SKIP_RELOCATE
  37. #define CONFIG_SPL_COMMON_INIT_DDR
  38. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  39. #endif
  40. #endif
  41. #endif /* CONFIG_RAMBOOT_PBL */
  42. #define CONFIG_DDR_ECC
  43. /* High Level Configuration Options */
  44. #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  45. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  46. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  47. #endif
  48. #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  49. #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  50. #define CONFIG_PCIE1 /* PCIE controller 1 */
  51. #define CONFIG_PCIE2 /* PCIE controller 2 */
  52. #define CONFIG_PCIE3 /* PCIE controller 3 */
  53. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  54. #define CONFIG_ENV_OVERWRITE
  55. /*
  56. * These can be toggled for performance analysis, otherwise use default.
  57. */
  58. #define CONFIG_SYS_CACHE_STASHING
  59. #define CONFIG_BTB /* toggle branch predition */
  60. #ifdef CONFIG_DDR_ECC
  61. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  62. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  63. #endif
  64. #define CONFIG_ENABLE_36BIT_PHYS
  65. #define CONFIG_ADDR_MAP
  66. #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
  67. #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
  68. #define CONFIG_SYS_MEMTEST_END 0x00400000
  69. /*
  70. * Config the L3 Cache as L3 SRAM
  71. */
  72. #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
  73. #define CONFIG_SYS_L3_SIZE (512 << 10)
  74. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
  75. #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
  76. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
  77. #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
  78. #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
  79. #define CONFIG_SYS_DCSRBAR 0xf0000000
  80. #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  81. /*
  82. * DDR Setup
  83. */
  84. #define CONFIG_VERY_BIG_RAM
  85. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  86. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  87. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  88. #define CONFIG_CHIP_SELECTS_PER_CTRL 4
  89. #define CONFIG_DDR_SPD
  90. /*
  91. * IFC Definitions
  92. */
  93. #define CONFIG_SYS_FLASH_BASE 0xe0000000
  94. #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  95. #ifdef CONFIG_SPL_BUILD
  96. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  97. #else
  98. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  99. #endif
  100. #define CONFIG_HWCONFIG
  101. /* define to use L1 as initial stack */
  102. #define CONFIG_L1_INIT_RAM
  103. #define CONFIG_SYS_INIT_RAM_LOCK
  104. #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
  105. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  106. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
  107. /* The assembler doesn't like typecast */
  108. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  109. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  110. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  111. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  112. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  113. GENERATED_GBL_DATA_SIZE)
  114. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  115. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  116. #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
  117. /* Serial Port - controlled on board with jumper J8
  118. * open - index 2
  119. * shorted - index 1
  120. */
  121. #define CONFIG_SYS_NS16550_SERIAL
  122. #define CONFIG_SYS_NS16550_REG_SIZE 1
  123. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  124. #define CONFIG_SYS_BAUDRATE_TABLE \
  125. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  126. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
  127. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
  128. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
  129. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
  130. /* I2C */
  131. #define CONFIG_SYS_I2C
  132. #define CONFIG_SYS_I2C_FSL
  133. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  134. #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
  135. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  136. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
  137. /*
  138. * General PCI
  139. * Memory space is mapped 1-1, but I/O space must start from 0.
  140. */
  141. /* controller 1, direct to uli, tgtid 3, Base address 20000 */
  142. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  143. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  144. #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  145. #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  146. /* controller 2, Slot 2, tgtid 2, Base address 201000 */
  147. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  148. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  149. #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
  150. #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
  151. /* controller 3, Slot 1, tgtid 1, Base address 202000 */
  152. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
  153. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
  154. #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
  155. #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
  156. /* controller 4, Base address 203000 */
  157. #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
  158. #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
  159. #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
  160. #ifdef CONFIG_PCI
  161. #if !defined(CONFIG_DM_PCI)
  162. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  163. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  164. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  165. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  166. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  167. #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
  168. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
  169. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  170. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  171. #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  172. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
  173. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  174. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  175. #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
  176. #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
  177. #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
  178. #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
  179. #define CONFIG_PCI_INDIRECT_BRIDGE
  180. #endif
  181. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  182. #endif /* CONFIG_PCI */
  183. /* SATA */
  184. #ifdef CONFIG_FSL_SATA_V2
  185. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  186. #define CONFIG_SATA1
  187. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  188. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  189. #define CONFIG_SATA2
  190. #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  191. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  192. #define CONFIG_LBA48
  193. #endif
  194. #ifdef CONFIG_FMAN_ENET
  195. #define CONFIG_ETHPRIME "FM1@DTSEC1"
  196. #endif
  197. /*
  198. * Environment
  199. */
  200. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  201. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  202. /*
  203. * Command line configuration.
  204. */
  205. /*
  206. * Miscellaneous configurable options
  207. */
  208. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  209. /*
  210. * For booting Linux, the board info and command line data
  211. * have to be in the first 64 MB of memory, since this is
  212. * the maximum mapped by the Linux kernel during initialization.
  213. */
  214. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
  215. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  216. #ifdef CONFIG_CMD_KGDB
  217. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  218. #endif
  219. /*
  220. * Environment Configuration
  221. */
  222. #define CONFIG_ROOTPATH "/opt/nfsroot"
  223. #define CONFIG_BOOTFILE "uImage"
  224. #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
  225. /* default location for tftp and bootm */
  226. #define CONFIG_LOADADDR 1000000
  227. #define CONFIG_HVBOOT \
  228. "setenv bootargs config-addr=0x60000000; " \
  229. "bootm 0x01000000 - 0x00f00000"
  230. #if defined(CONFIG_SPIFLASH)
  231. #elif defined(CONFIG_SDCARD)
  232. #define CONFIG_SYS_MMC_ENV_DEV 0
  233. #endif
  234. #define CONFIG_SYS_CLK_FREQ 66666666
  235. #define CONFIG_DDR_CLK_FREQ 133333333
  236. #ifndef __ASSEMBLY__
  237. unsigned long get_board_sys_clk(void);
  238. unsigned long get_board_ddr_clk(void);
  239. #endif
  240. /*
  241. * DDR Setup
  242. */
  243. #define CONFIG_SYS_SPD_BUS_NUM 0
  244. #define SPD_EEPROM_ADDRESS1 0x52
  245. #define SPD_EEPROM_ADDRESS2 0x54
  246. #define SPD_EEPROM_ADDRESS3 0x56
  247. #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
  248. #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
  249. /*
  250. * IFC Definitions
  251. */
  252. #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
  253. #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  254. + 0x8000000) | \
  255. CSPR_PORT_SIZE_16 | \
  256. CSPR_MSEL_NOR | \
  257. CSPR_V)
  258. #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
  259. #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  260. CSPR_PORT_SIZE_16 | \
  261. CSPR_MSEL_NOR | \
  262. CSPR_V)
  263. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  264. /* NOR Flash Timing Params */
  265. #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
  266. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  267. FTIM0_NOR_TEADC(0x5) | \
  268. FTIM0_NOR_TEAHC(0x5))
  269. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  270. FTIM1_NOR_TRAD_NOR(0x1A) |\
  271. FTIM1_NOR_TSEQRAD_NOR(0x13))
  272. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  273. FTIM2_NOR_TCH(0x4) | \
  274. FTIM2_NOR_TWPH(0x0E) | \
  275. FTIM2_NOR_TWP(0x1c))
  276. #define CONFIG_SYS_NOR_FTIM3 0x0
  277. #define CONFIG_SYS_FLASH_QUIET_TEST
  278. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  279. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  280. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  281. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  282. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  283. #define CONFIG_SYS_FLASH_EMPTY_INFO
  284. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
  285. + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
  286. /* NAND Flash on IFC */
  287. #define CONFIG_NAND_FSL_IFC
  288. #define CONFIG_SYS_NAND_MAX_ECCPOS 256
  289. #define CONFIG_SYS_NAND_MAX_OOBFREE 2
  290. #define CONFIG_SYS_NAND_BASE 0xff800000
  291. #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
  292. #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
  293. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  294. | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  295. | CSPR_MSEL_NAND /* MSEL = NAND */ \
  296. | CSPR_V)
  297. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  298. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  299. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  300. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  301. | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
  302. | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
  303. | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
  304. | CSOR_NAND_PB(128)) /*Page Per Block = 128*/
  305. #define CONFIG_SYS_NAND_ONFI_DETECTION
  306. /* ONFI NAND Flash mode0 Timing Params */
  307. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
  308. FTIM0_NAND_TWP(0x18) | \
  309. FTIM0_NAND_TWCHT(0x07) | \
  310. FTIM0_NAND_TWH(0x0a))
  311. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  312. FTIM1_NAND_TWBE(0x39) | \
  313. FTIM1_NAND_TRR(0x0e) | \
  314. FTIM1_NAND_TRP(0x18))
  315. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  316. FTIM2_NAND_TREH(0x0a) | \
  317. FTIM2_NAND_TWHRE(0x1e))
  318. #define CONFIG_SYS_NAND_FTIM3 0x0
  319. #define CONFIG_SYS_NAND_DDR_LAW 11
  320. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  321. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  322. #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
  323. #if defined(CONFIG_MTD_RAW_NAND)
  324. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  325. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  326. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  327. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  328. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  329. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  330. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  331. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  332. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
  333. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
  334. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
  335. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
  336. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
  337. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
  338. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
  339. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
  340. #else
  341. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  342. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
  343. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  344. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  345. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  346. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  347. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  348. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  349. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
  350. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
  351. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
  352. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
  353. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
  354. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
  355. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
  356. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
  357. #endif
  358. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
  359. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
  360. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
  361. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
  362. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
  363. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
  364. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
  365. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
  366. /* CPLD on IFC */
  367. #define CONFIG_SYS_CPLD_BASE 0xffdf0000
  368. #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
  369. #define CONFIG_SYS_CSPR3_EXT (0xf)
  370. #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
  371. | CSPR_PORT_SIZE_8 \
  372. | CSPR_MSEL_GPCM \
  373. | CSPR_V)
  374. #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
  375. #define CONFIG_SYS_CSOR3 0x0
  376. /* CPLD Timing parameters for IFC CS3 */
  377. #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  378. FTIM0_GPCM_TEADC(0x0e) | \
  379. FTIM0_GPCM_TEAHC(0x0e))
  380. #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
  381. FTIM1_GPCM_TRAD(0x1f))
  382. #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
  383. FTIM2_GPCM_TCH(0x8) | \
  384. FTIM2_GPCM_TWP(0x1f))
  385. #define CONFIG_SYS_CS3_FTIM3 0x0
  386. #if defined(CONFIG_RAMBOOT_PBL)
  387. #define CONFIG_SYS_RAMBOOT
  388. #endif
  389. /* I2C */
  390. #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */
  391. #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */
  392. #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
  393. #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
  394. #define I2C_MUX_CH_DEFAULT 0x8
  395. #define I2C_MUX_CH_VOL_MONITOR 0xa
  396. #define I2C_MUX_CH_VSC3316_FS 0xc
  397. #define I2C_MUX_CH_VSC3316_BS 0xd
  398. /* Voltage monitor on channel 2*/
  399. #define I2C_VOL_MONITOR_ADDR 0x40
  400. #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
  401. #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
  402. #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
  403. #define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv"
  404. #ifndef CONFIG_SPL_BUILD
  405. #define CONFIG_VID
  406. #endif
  407. #define CONFIG_VOL_MONITOR_IR36021_SET
  408. #define CONFIG_VOL_MONITOR_IR36021_READ
  409. /* The lowest and highest voltage allowed for T4240RDB */
  410. #define VDD_MV_MIN 819
  411. #define VDD_MV_MAX 1212
  412. /*
  413. * eSPI - Enhanced SPI
  414. */
  415. /* Qman/Bman */
  416. #ifndef CONFIG_NOBQFMAN
  417. #define CONFIG_SYS_BMAN_NUM_PORTALS 50
  418. #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  419. #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  420. #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
  421. #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
  422. #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
  423. #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
  424. #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  425. #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
  426. CONFIG_SYS_BMAN_CENA_SIZE)
  427. #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  428. #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
  429. #define CONFIG_SYS_QMAN_NUM_PORTALS 50
  430. #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
  431. #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
  432. #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
  433. #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
  434. #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
  435. #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
  436. #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  437. #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
  438. CONFIG_SYS_QMAN_CENA_SIZE)
  439. #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  440. #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
  441. #define CONFIG_SYS_DPAA_FMAN
  442. #define CONFIG_SYS_DPAA_PME
  443. #define CONFIG_SYS_PMAN
  444. #define CONFIG_SYS_DPAA_DCE
  445. #define CONFIG_SYS_DPAA_RMAN
  446. #define CONFIG_SYS_INTERLAKEN
  447. /* Default address of microcode for the Linux Fman driver */
  448. #if defined(CONFIG_SPIFLASH)
  449. /*
  450. * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  451. * env, so we got 0x110000.
  452. */
  453. #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
  454. #elif defined(CONFIG_SDCARD)
  455. /*
  456. * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  457. * about 1MB (2048 blocks), Env is stored after the image, and the env size is
  458. * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
  459. */
  460. #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
  461. #elif defined(CONFIG_MTD_RAW_NAND)
  462. #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
  463. #else
  464. #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
  465. #endif
  466. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  467. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  468. #endif /* CONFIG_NOBQFMAN */
  469. #ifdef CONFIG_SYS_DPAA_FMAN
  470. #define CONFIG_PHYLIB_10G
  471. #define CONFIG_PHY_VITESSE
  472. #define CONFIG_CORTINA_FW_ADDR 0xefe00000
  473. #define CONFIG_CORTINA_FW_LENGTH 0x40000
  474. #define CONFIG_PHY_TERANETICS
  475. #define SGMII_PHY_ADDR1 0x0
  476. #define SGMII_PHY_ADDR2 0x1
  477. #define SGMII_PHY_ADDR3 0x2
  478. #define SGMII_PHY_ADDR4 0x3
  479. #define SGMII_PHY_ADDR5 0x4
  480. #define SGMII_PHY_ADDR6 0x5
  481. #define SGMII_PHY_ADDR7 0x6
  482. #define SGMII_PHY_ADDR8 0x7
  483. #define FM1_10GEC1_PHY_ADDR 0x10
  484. #define FM1_10GEC2_PHY_ADDR 0x11
  485. #define FM2_10GEC1_PHY_ADDR 0x12
  486. #define FM2_10GEC2_PHY_ADDR 0x13
  487. #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR
  488. #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR
  489. #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR
  490. #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR
  491. #endif
  492. /* SATA */
  493. #ifdef CONFIG_FSL_SATA_V2
  494. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  495. #define CONFIG_SATA1
  496. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  497. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  498. #define CONFIG_SATA2
  499. #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  500. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  501. #define CONFIG_LBA48
  502. #endif
  503. #ifdef CONFIG_FMAN_ENET
  504. #define CONFIG_ETHPRIME "FM1@DTSEC1"
  505. #endif
  506. /*
  507. * USB
  508. */
  509. #define CONFIG_USB_EHCI_FSL
  510. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  511. #define CONFIG_HAS_FSL_DR_USB
  512. #ifdef CONFIG_MMC
  513. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  514. #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
  515. #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
  516. #endif
  517. #define __USB_PHY_TYPE utmi
  518. /*
  519. * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
  520. * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
  521. * interleaving. It can be cacheline, page, bank, superbank.
  522. * See doc/README.fsl-ddr for details.
  523. */
  524. #ifdef CONFIG_ARCH_T4240
  525. #define CTRL_INTLV_PREFERED 3way_4KB
  526. #else
  527. #define CTRL_INTLV_PREFERED cacheline
  528. #endif
  529. #define CONFIG_EXTRA_ENV_SETTINGS \
  530. "hwconfig=fsl_ddr:" \
  531. "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
  532. "bank_intlv=auto;" \
  533. "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
  534. "netdev=eth0\0" \
  535. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  536. "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  537. "tftpflash=tftpboot $loadaddr $uboot && " \
  538. "protect off $ubootaddr +$filesize && " \
  539. "erase $ubootaddr +$filesize && " \
  540. "cp.b $loadaddr $ubootaddr $filesize && " \
  541. "protect on $ubootaddr +$filesize && " \
  542. "cmp.b $loadaddr $ubootaddr $filesize\0" \
  543. "consoledev=ttyS0\0" \
  544. "ramdiskaddr=2000000\0" \
  545. "ramdiskfile=t4240rdb/ramdisk.uboot\0" \
  546. "fdtaddr=1e00000\0" \
  547. "fdtfile=t4240rdb/t4240rdb.dtb\0" \
  548. "bdev=sda3\0"
  549. #define CONFIG_HVBOOT \
  550. "setenv bootargs config-addr=0x60000000; " \
  551. "bootm 0x01000000 - 0x00f00000"
  552. #define CONFIG_LINUX \
  553. "setenv bootargs root=/dev/ram rw " \
  554. "console=$consoledev,$baudrate $othbootargs;" \
  555. "setenv ramdiskaddr 0x02000000;" \
  556. "setenv fdtaddr 0x00c00000;" \
  557. "setenv loadaddr 0x1000000;" \
  558. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  559. #define CONFIG_HDBOOT \
  560. "setenv bootargs root=/dev/$bdev rw " \
  561. "console=$consoledev,$baudrate $othbootargs;" \
  562. "tftp $loadaddr $bootfile;" \
  563. "tftp $fdtaddr $fdtfile;" \
  564. "bootm $loadaddr - $fdtaddr"
  565. #define CONFIG_NFSBOOTCOMMAND \
  566. "setenv bootargs root=/dev/nfs rw " \
  567. "nfsroot=$serverip:$rootpath " \
  568. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  569. "console=$consoledev,$baudrate $othbootargs;" \
  570. "tftp $loadaddr $bootfile;" \
  571. "tftp $fdtaddr $fdtfile;" \
  572. "bootm $loadaddr - $fdtaddr"
  573. #define CONFIG_RAMBOOTCOMMAND \
  574. "setenv bootargs root=/dev/ram rw " \
  575. "console=$consoledev,$baudrate $othbootargs;" \
  576. "tftp $ramdiskaddr $ramdiskfile;" \
  577. "tftp $loadaddr $bootfile;" \
  578. "tftp $fdtaddr $fdtfile;" \
  579. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  580. #define CONFIG_BOOTCOMMAND CONFIG_LINUX
  581. #include <asm/fsl_secure_boot.h>
  582. #endif /* __CONFIG_H */