T4240QDS.h 18 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2011-2012 Freescale Semiconductor, Inc.
  4. */
  5. /*
  6. * T4240 QDS board configuration file
  7. */
  8. #ifndef __CONFIG_H
  9. #define __CONFIG_H
  10. #define CONFIG_FSL_SATA_V2
  11. #define CONFIG_PCIE4
  12. #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
  13. #ifdef CONFIG_RAMBOOT_PBL
  14. #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg
  15. #if !defined(CONFIG_MTD_RAW_NAND) && !defined(CONFIG_SDCARD)
  16. #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
  17. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  18. #else
  19. #define CONFIG_SPL_FLUSH_IMAGE
  20. #define CONFIG_SPL_PAD_TO 0x40000
  21. #define CONFIG_SPL_MAX_SIZE 0x28000
  22. #define RESET_VECTOR_OFFSET 0x27FFC
  23. #define BOOT_PAGE_OFFSET 0x27000
  24. #ifdef CONFIG_MTD_RAW_NAND
  25. #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
  26. #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
  27. #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
  28. #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
  29. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_nand_rcw.cfg
  30. #endif
  31. #ifdef CONFIG_SDCARD
  32. #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
  33. #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
  34. #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
  35. #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
  36. #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
  37. #ifndef CONFIG_SPL_BUILD
  38. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  39. #endif
  40. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_sd_rcw.cfg
  41. #endif
  42. #ifdef CONFIG_SPL_BUILD
  43. #define CONFIG_SPL_SKIP_RELOCATE
  44. #define CONFIG_SPL_COMMON_INIT_DDR
  45. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  46. #endif
  47. #endif
  48. #endif /* CONFIG_RAMBOOT_PBL */
  49. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  50. /* Set 1M boot space */
  51. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  52. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  53. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  54. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  55. #endif
  56. #define CONFIG_SRIO_PCIE_BOOT_MASTER
  57. #define CONFIG_DDR_ECC
  58. #include "t4qds.h"
  59. #if defined(CONFIG_SPIFLASH)
  60. #elif defined(CONFIG_SDCARD)
  61. #define CONFIG_SYS_MMC_ENV_DEV 0
  62. #endif
  63. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
  64. #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
  65. #ifndef __ASSEMBLY__
  66. unsigned long get_board_sys_clk(void);
  67. unsigned long get_board_ddr_clk(void);
  68. #endif
  69. /* EEPROM */
  70. #define CONFIG_ID_EEPROM
  71. #define CONFIG_SYS_I2C_EEPROM_NXID
  72. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  73. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  74. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  75. /*
  76. * DDR Setup
  77. */
  78. #define CONFIG_SYS_SPD_BUS_NUM 0
  79. #define SPD_EEPROM_ADDRESS1 0x51
  80. #define SPD_EEPROM_ADDRESS2 0x52
  81. #define SPD_EEPROM_ADDRESS3 0x53
  82. #define SPD_EEPROM_ADDRESS4 0x54
  83. #define SPD_EEPROM_ADDRESS5 0x55
  84. #define SPD_EEPROM_ADDRESS6 0x56
  85. #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
  86. #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
  87. /*
  88. * IFC Definitions
  89. */
  90. #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
  91. #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  92. + 0x8000000) | \
  93. CSPR_PORT_SIZE_16 | \
  94. CSPR_MSEL_NOR | \
  95. CSPR_V)
  96. #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
  97. #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  98. CSPR_PORT_SIZE_16 | \
  99. CSPR_MSEL_NOR | \
  100. CSPR_V)
  101. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  102. /* NOR Flash Timing Params */
  103. #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
  104. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  105. FTIM0_NOR_TEADC(0x5) | \
  106. FTIM0_NOR_TEAHC(0x5))
  107. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  108. FTIM1_NOR_TRAD_NOR(0x1A) |\
  109. FTIM1_NOR_TSEQRAD_NOR(0x13))
  110. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  111. FTIM2_NOR_TCH(0x4) | \
  112. FTIM2_NOR_TWPH(0x0E) | \
  113. FTIM2_NOR_TWP(0x1c))
  114. #define CONFIG_SYS_NOR_FTIM3 0x0
  115. #define CONFIG_SYS_FLASH_QUIET_TEST
  116. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  117. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  118. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  119. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  120. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  121. #define CONFIG_SYS_FLASH_EMPTY_INFO
  122. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
  123. + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
  124. #define CONFIG_FSL_QIXIS /* use common QIXIS code */
  125. #define QIXIS_BASE 0xffdf0000
  126. #define QIXIS_LBMAP_SWITCH 6
  127. #define QIXIS_LBMAP_MASK 0x0f
  128. #define QIXIS_LBMAP_SHIFT 0
  129. #define QIXIS_LBMAP_DFLTBANK 0x00
  130. #define QIXIS_LBMAP_ALTBANK 0x04
  131. #define QIXIS_RST_CTL_RESET 0x83
  132. #define QIXIS_RST_FORCE_MEM 0x1
  133. #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  134. #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  135. #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  136. #define QIXIS_BRDCFG5 0x55
  137. #define QIXIS_MUX_SDHC 2
  138. #define QIXIS_MUX_SDHC_WIDTH8 1
  139. #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
  140. #define CONFIG_SYS_CSPR3_EXT (0xf)
  141. #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
  142. | CSPR_PORT_SIZE_8 \
  143. | CSPR_MSEL_GPCM \
  144. | CSPR_V)
  145. #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
  146. #define CONFIG_SYS_CSOR3 0x0
  147. /* QIXIS Timing parameters for IFC CS3 */
  148. #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  149. FTIM0_GPCM_TEADC(0x0e) | \
  150. FTIM0_GPCM_TEAHC(0x0e))
  151. #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
  152. FTIM1_GPCM_TRAD(0x3f))
  153. #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
  154. FTIM2_GPCM_TCH(0x8) | \
  155. FTIM2_GPCM_TWP(0x1f))
  156. #define CONFIG_SYS_CS3_FTIM3 0x0
  157. /* NAND Flash on IFC */
  158. #define CONFIG_NAND_FSL_IFC
  159. #define CONFIG_SYS_NAND_BASE 0xff800000
  160. #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
  161. #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
  162. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  163. | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  164. | CSPR_MSEL_NAND /* MSEL = NAND */ \
  165. | CSPR_V)
  166. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  167. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  168. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  169. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  170. | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
  171. | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
  172. | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
  173. | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  174. #define CONFIG_SYS_NAND_ONFI_DETECTION
  175. /* ONFI NAND Flash mode0 Timing Params */
  176. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
  177. FTIM0_NAND_TWP(0x18) | \
  178. FTIM0_NAND_TWCHT(0x07) | \
  179. FTIM0_NAND_TWH(0x0a))
  180. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  181. FTIM1_NAND_TWBE(0x39) | \
  182. FTIM1_NAND_TRR(0x0e) | \
  183. FTIM1_NAND_TRP(0x18))
  184. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  185. FTIM2_NAND_TREH(0x0a) | \
  186. FTIM2_NAND_TWHRE(0x1e))
  187. #define CONFIG_SYS_NAND_FTIM3 0x0
  188. #define CONFIG_SYS_NAND_DDR_LAW 11
  189. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  190. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  191. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  192. #define CONFIG_SYS_NAND_MAX_OOBFREE 2
  193. #define CONFIG_SYS_NAND_MAX_ECCPOS 256
  194. #if defined(CONFIG_MTD_RAW_NAND)
  195. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  196. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  197. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  198. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  199. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  200. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  201. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  202. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  203. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
  204. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
  205. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  206. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  207. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  208. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  209. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  210. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  211. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
  212. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
  213. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
  214. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
  215. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
  216. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
  217. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
  218. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
  219. #else
  220. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  221. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
  222. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  223. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  224. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  225. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  226. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  227. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  228. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
  229. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
  230. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  231. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  232. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  233. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  234. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  235. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  236. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
  237. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
  238. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
  239. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
  240. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
  241. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
  242. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
  243. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
  244. #endif
  245. #if defined(CONFIG_RAMBOOT_PBL)
  246. #define CONFIG_SYS_RAMBOOT
  247. #endif
  248. /* I2C */
  249. #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */
  250. #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */
  251. #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
  252. #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
  253. #define I2C_MUX_CH_DEFAULT 0x8
  254. #define I2C_MUX_CH_VOL_MONITOR 0xa
  255. #define I2C_MUX_CH_VSC3316_FS 0xc
  256. #define I2C_MUX_CH_VSC3316_BS 0xd
  257. /* Voltage monitor on channel 2*/
  258. #define I2C_VOL_MONITOR_ADDR 0x40
  259. #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
  260. #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
  261. #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
  262. /* VSC Crossbar switches */
  263. #define CONFIG_VSC_CROSSBAR
  264. #define VSC3316_FSM_TX_ADDR 0x70
  265. #define VSC3316_FSM_RX_ADDR 0x71
  266. /*
  267. * RapidIO
  268. */
  269. /*
  270. * for slave u-boot IMAGE instored in master memory space,
  271. * PHYS must be aligned based on the SIZE
  272. */
  273. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
  274. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
  275. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
  276. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
  277. /*
  278. * for slave UCODE and ENV instored in master memory space,
  279. * PHYS must be aligned based on the SIZE
  280. */
  281. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
  282. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
  283. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
  284. /* slave core release by master*/
  285. #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
  286. #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
  287. /*
  288. * SRIO_PCIE_BOOT - SLAVE
  289. */
  290. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  291. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
  292. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
  293. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
  294. #endif
  295. /*
  296. * eSPI - Enhanced SPI
  297. */
  298. /* Qman/Bman */
  299. #ifndef CONFIG_NOBQFMAN
  300. #define CONFIG_SYS_BMAN_NUM_PORTALS 50
  301. #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  302. #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  303. #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
  304. #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
  305. #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
  306. #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
  307. #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  308. #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
  309. CONFIG_SYS_BMAN_CENA_SIZE)
  310. #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  311. #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
  312. #define CONFIG_SYS_QMAN_NUM_PORTALS 50
  313. #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
  314. #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
  315. #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
  316. #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
  317. #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
  318. #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
  319. #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  320. #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
  321. CONFIG_SYS_QMAN_CENA_SIZE)
  322. #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  323. #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
  324. #define CONFIG_SYS_DPAA_FMAN
  325. #define CONFIG_SYS_DPAA_PME
  326. #define CONFIG_SYS_PMAN
  327. #define CONFIG_SYS_DPAA_DCE
  328. #define CONFIG_SYS_DPAA_RMAN
  329. #define CONFIG_SYS_INTERLAKEN
  330. /* Default address of microcode for the Linux Fman driver */
  331. #if defined(CONFIG_SPIFLASH)
  332. /*
  333. * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  334. * env, so we got 0x110000.
  335. */
  336. #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
  337. #elif defined(CONFIG_SDCARD)
  338. /*
  339. * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  340. * about 1MB (2048 blocks), Env is stored after the image, and the env size is
  341. * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
  342. */
  343. #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
  344. #elif defined(CONFIG_MTD_RAW_NAND)
  345. #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
  346. #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  347. /*
  348. * Slave has no ucode locally, it can fetch this from remote. When implementing
  349. * in two corenet boards, slave's ucode could be stored in master's memory
  350. * space, the address can be mapped from slave TLB->slave LAW->
  351. * slave SRIO or PCIE outbound window->master inbound window->
  352. * master LAW->the ucode address in master's memory space.
  353. */
  354. #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
  355. #else
  356. #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
  357. #endif
  358. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  359. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  360. #endif /* CONFIG_NOBQFMAN */
  361. #ifdef CONFIG_SYS_DPAA_FMAN
  362. #define CONFIG_PHYLIB_10G
  363. #define CONFIG_PHY_VITESSE
  364. #define CONFIG_PHY_TERANETICS
  365. #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  366. #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
  367. #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  368. #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  369. #define FM1_10GEC1_PHY_ADDR 0x0
  370. #define FM1_10GEC2_PHY_ADDR 0x1
  371. #define FM2_10GEC1_PHY_ADDR 0x2
  372. #define FM2_10GEC2_PHY_ADDR 0x3
  373. #endif
  374. /* SATA */
  375. #ifdef CONFIG_FSL_SATA_V2
  376. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  377. #define CONFIG_SATA1
  378. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  379. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  380. #define CONFIG_SATA2
  381. #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  382. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  383. #define CONFIG_LBA48
  384. #endif
  385. #ifdef CONFIG_FMAN_ENET
  386. #define CONFIG_ETHPRIME "FM1@DTSEC1"
  387. #endif
  388. /*
  389. * USB
  390. */
  391. #define CONFIG_USB_EHCI_FSL
  392. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  393. #define CONFIG_HAS_FSL_DR_USB
  394. #ifdef CONFIG_MMC
  395. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  396. #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
  397. #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
  398. #define CONFIG_ESDHC_DETECT_QUIRK \
  399. (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \
  400. IS_SVR_REV(get_svr(), 1, 0))
  401. #define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \
  402. (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8))
  403. #endif
  404. #define __USB_PHY_TYPE utmi
  405. /*
  406. * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
  407. * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
  408. * interleaving. It can be cacheline, page, bank, superbank.
  409. * See doc/README.fsl-ddr for details.
  410. */
  411. #ifdef CONFIG_ARCH_T4240
  412. #define CTRL_INTLV_PREFERED 3way_4KB
  413. #else
  414. #define CTRL_INTLV_PREFERED cacheline
  415. #endif
  416. #define CONFIG_EXTRA_ENV_SETTINGS \
  417. "hwconfig=fsl_ddr:" \
  418. "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
  419. "bank_intlv=auto;" \
  420. "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
  421. "netdev=eth0\0" \
  422. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  423. "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  424. "tftpflash=tftpboot $loadaddr $uboot && " \
  425. "protect off $ubootaddr +$filesize && " \
  426. "erase $ubootaddr +$filesize && " \
  427. "cp.b $loadaddr $ubootaddr $filesize && " \
  428. "protect on $ubootaddr +$filesize && " \
  429. "cmp.b $loadaddr $ubootaddr $filesize\0" \
  430. "consoledev=ttyS0\0" \
  431. "ramdiskaddr=2000000\0" \
  432. "ramdiskfile=t4240qds/ramdisk.uboot\0" \
  433. "fdtaddr=1e00000\0" \
  434. "fdtfile=t4240qds/t4240qds.dtb\0" \
  435. "bdev=sda3\0"
  436. #define CONFIG_HVBOOT \
  437. "setenv bootargs config-addr=0x60000000; " \
  438. "bootm 0x01000000 - 0x00f00000"
  439. #define CONFIG_ALU \
  440. "setenv bootargs root=/dev/$bdev rw " \
  441. "console=$consoledev,$baudrate $othbootargs;" \
  442. "cpu 1 release 0x01000000 - - -;" \
  443. "cpu 2 release 0x01000000 - - -;" \
  444. "cpu 3 release 0x01000000 - - -;" \
  445. "cpu 4 release 0x01000000 - - -;" \
  446. "cpu 5 release 0x01000000 - - -;" \
  447. "cpu 6 release 0x01000000 - - -;" \
  448. "cpu 7 release 0x01000000 - - -;" \
  449. "go 0x01000000"
  450. #define CONFIG_LINUX \
  451. "setenv bootargs root=/dev/ram rw " \
  452. "console=$consoledev,$baudrate $othbootargs;" \
  453. "setenv ramdiskaddr 0x02000000;" \
  454. "setenv fdtaddr 0x00c00000;" \
  455. "setenv loadaddr 0x1000000;" \
  456. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  457. #define CONFIG_HDBOOT \
  458. "setenv bootargs root=/dev/$bdev rw " \
  459. "console=$consoledev,$baudrate $othbootargs;" \
  460. "tftp $loadaddr $bootfile;" \
  461. "tftp $fdtaddr $fdtfile;" \
  462. "bootm $loadaddr - $fdtaddr"
  463. #define CONFIG_NFSBOOTCOMMAND \
  464. "setenv bootargs root=/dev/nfs rw " \
  465. "nfsroot=$serverip:$rootpath " \
  466. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  467. "console=$consoledev,$baudrate $othbootargs;" \
  468. "tftp $loadaddr $bootfile;" \
  469. "tftp $fdtaddr $fdtfile;" \
  470. "bootm $loadaddr - $fdtaddr"
  471. #define CONFIG_RAMBOOTCOMMAND \
  472. "setenv bootargs root=/dev/ram rw " \
  473. "console=$consoledev,$baudrate $othbootargs;" \
  474. "tftp $ramdiskaddr $ramdiskfile;" \
  475. "tftp $loadaddr $bootfile;" \
  476. "tftp $fdtaddr $fdtfile;" \
  477. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  478. #define CONFIG_BOOTCOMMAND CONFIG_LINUX
  479. #include <asm/fsl_secure_boot.h>
  480. #endif /* __CONFIG_H */