T208xRDB.h 24 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. */
  5. /*
  6. * T2080 RDB/PCIe board configuration file
  7. */
  8. #ifndef __T2080RDB_H
  9. #define __T2080RDB_H
  10. #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
  11. #define CONFIG_FSL_SATA_V2
  12. /* High Level Configuration Options */
  13. #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  14. #define CONFIG_ENABLE_36BIT_PHYS
  15. #ifdef CONFIG_PHYS_64BIT
  16. #define CONFIG_ADDR_MAP 1
  17. #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
  18. #endif
  19. #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  20. #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  21. #define CONFIG_ENV_OVERWRITE
  22. #ifdef CONFIG_RAMBOOT_PBL
  23. #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
  24. #define CONFIG_SPL_FLUSH_IMAGE
  25. #define CONFIG_SPL_PAD_TO 0x40000
  26. #define CONFIG_SPL_MAX_SIZE 0x28000
  27. #define RESET_VECTOR_OFFSET 0x27FFC
  28. #define BOOT_PAGE_OFFSET 0x27000
  29. #ifdef CONFIG_SPL_BUILD
  30. #define CONFIG_SPL_SKIP_RELOCATE
  31. #define CONFIG_SPL_COMMON_INIT_DDR
  32. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  33. #endif
  34. #ifdef CONFIG_MTD_RAW_NAND
  35. #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
  36. #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
  37. #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
  38. #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
  39. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg
  40. #endif
  41. #ifdef CONFIG_SPIFLASH
  42. #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
  43. #define CONFIG_SPL_SPI_FLASH_MINIMAL
  44. #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
  45. #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
  46. #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
  47. #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
  48. #ifndef CONFIG_SPL_BUILD
  49. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  50. #endif
  51. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg
  52. #endif
  53. #ifdef CONFIG_SDCARD
  54. #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
  55. #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
  56. #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
  57. #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
  58. #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
  59. #ifndef CONFIG_SPL_BUILD
  60. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  61. #endif
  62. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg
  63. #endif
  64. #endif /* CONFIG_RAMBOOT_PBL */
  65. #define CONFIG_SRIO_PCIE_BOOT_MASTER
  66. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  67. /* Set 1M boot space */
  68. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  69. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  70. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  71. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  72. #endif
  73. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  74. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  75. #endif
  76. /*
  77. * These can be toggled for performance analysis, otherwise use default.
  78. */
  79. #define CONFIG_SYS_CACHE_STASHING
  80. #define CONFIG_BTB /* toggle branch predition */
  81. #define CONFIG_DDR_ECC
  82. #ifdef CONFIG_DDR_ECC
  83. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  84. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  85. #endif
  86. #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
  87. #define CONFIG_SYS_MEMTEST_END 0x00400000
  88. #if defined(CONFIG_SPIFLASH)
  89. #elif defined(CONFIG_SDCARD)
  90. #define CONFIG_SYS_MMC_ENV_DEV 0
  91. #endif
  92. #ifndef __ASSEMBLY__
  93. unsigned long get_board_sys_clk(void);
  94. unsigned long get_board_ddr_clk(void);
  95. #endif
  96. #define CONFIG_SYS_CLK_FREQ 66660000
  97. #define CONFIG_DDR_CLK_FREQ 133330000
  98. /*
  99. * Config the L3 Cache as L3 SRAM
  100. */
  101. #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
  102. #define CONFIG_SYS_L3_SIZE (512 << 10)
  103. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
  104. #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
  105. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
  106. #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
  107. #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
  108. #define CONFIG_SYS_DCSRBAR 0xf0000000
  109. #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  110. /* EEPROM */
  111. #define CONFIG_ID_EEPROM
  112. #define CONFIG_SYS_I2C_EEPROM_NXID
  113. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  114. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
  115. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  116. /*
  117. * DDR Setup
  118. */
  119. #define CONFIG_VERY_BIG_RAM
  120. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  121. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  122. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  123. #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
  124. #define CONFIG_DDR_SPD
  125. #define CONFIG_SYS_SPD_BUS_NUM 0
  126. #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
  127. #define SPD_EEPROM_ADDRESS1 0x51
  128. #define SPD_EEPROM_ADDRESS2 0x52
  129. #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
  130. #define CTRL_INTLV_PREFERED cacheline
  131. /*
  132. * IFC Definitions
  133. */
  134. #define CONFIG_SYS_FLASH_BASE 0xe8000000
  135. #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  136. #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
  137. #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  138. CSPR_PORT_SIZE_16 | \
  139. CSPR_MSEL_NOR | \
  140. CSPR_V)
  141. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  142. /* NOR Flash Timing Params */
  143. #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
  144. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  145. FTIM0_NOR_TEADC(0x5) | \
  146. FTIM0_NOR_TEAHC(0x5))
  147. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  148. FTIM1_NOR_TRAD_NOR(0x1A) |\
  149. FTIM1_NOR_TSEQRAD_NOR(0x13))
  150. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  151. FTIM2_NOR_TCH(0x4) | \
  152. FTIM2_NOR_TWPH(0x0E) | \
  153. FTIM2_NOR_TWP(0x1c))
  154. #define CONFIG_SYS_NOR_FTIM3 0x0
  155. #define CONFIG_SYS_FLASH_QUIET_TEST
  156. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  157. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  158. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  159. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  160. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  161. #define CONFIG_SYS_FLASH_EMPTY_INFO
  162. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS }
  163. /* CPLD on IFC */
  164. #define CONFIG_SYS_CPLD_BASE 0xffdf0000
  165. #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
  166. #define CONFIG_SYS_CSPR2_EXT (0xf)
  167. #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
  168. | CSPR_PORT_SIZE_8 \
  169. | CSPR_MSEL_GPCM \
  170. | CSPR_V)
  171. #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
  172. #define CONFIG_SYS_CSOR2 0x0
  173. /* CPLD Timing parameters for IFC CS2 */
  174. #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  175. FTIM0_GPCM_TEADC(0x0e) | \
  176. FTIM0_GPCM_TEAHC(0x0e))
  177. #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
  178. FTIM1_GPCM_TRAD(0x1f))
  179. #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
  180. FTIM2_GPCM_TCH(0x8) | \
  181. FTIM2_GPCM_TWP(0x1f))
  182. #define CONFIG_SYS_CS2_FTIM3 0x0
  183. /* NAND Flash on IFC */
  184. #define CONFIG_NAND_FSL_IFC
  185. #define CONFIG_SYS_NAND_BASE 0xff800000
  186. #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
  187. #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
  188. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  189. | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  190. | CSPR_MSEL_NAND /* MSEL = NAND */ \
  191. | CSPR_V)
  192. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  193. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  194. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  195. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  196. | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
  197. | CSOR_NAND_PGS_2K /* Page Size = 2K */\
  198. | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
  199. | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  200. #define CONFIG_SYS_NAND_ONFI_DETECTION
  201. /* ONFI NAND Flash mode0 Timing Params */
  202. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
  203. FTIM0_NAND_TWP(0x18) | \
  204. FTIM0_NAND_TWCHT(0x07) | \
  205. FTIM0_NAND_TWH(0x0a))
  206. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  207. FTIM1_NAND_TWBE(0x39) | \
  208. FTIM1_NAND_TRR(0x0e) | \
  209. FTIM1_NAND_TRP(0x18))
  210. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  211. FTIM2_NAND_TREH(0x0a) | \
  212. FTIM2_NAND_TWHRE(0x1e))
  213. #define CONFIG_SYS_NAND_FTIM3 0x0
  214. #define CONFIG_SYS_NAND_DDR_LAW 11
  215. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  216. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  217. #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
  218. #if defined(CONFIG_MTD_RAW_NAND)
  219. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  220. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  221. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  222. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  223. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  224. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  225. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  226. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  227. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
  228. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
  229. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  230. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  231. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  232. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  233. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  234. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  235. #else
  236. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  237. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
  238. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  239. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  240. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  241. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  242. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  243. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  244. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
  245. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
  246. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
  247. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
  248. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
  249. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
  250. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
  251. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
  252. #endif
  253. #if defined(CONFIG_RAMBOOT_PBL)
  254. #define CONFIG_SYS_RAMBOOT
  255. #endif
  256. #ifdef CONFIG_SPL_BUILD
  257. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  258. #else
  259. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  260. #endif
  261. #define CONFIG_HWCONFIG
  262. /* define to use L1 as initial stack */
  263. #define CONFIG_L1_INIT_RAM
  264. #define CONFIG_SYS_INIT_RAM_LOCK
  265. #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
  266. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  267. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
  268. /* The assembler doesn't like typecast */
  269. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  270. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  271. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  272. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  273. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  274. GENERATED_GBL_DATA_SIZE)
  275. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  276. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  277. #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
  278. /*
  279. * Serial Port
  280. */
  281. #define CONFIG_SYS_NS16550_SERIAL
  282. #define CONFIG_SYS_NS16550_REG_SIZE 1
  283. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  284. #define CONFIG_SYS_BAUDRATE_TABLE \
  285. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  286. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
  287. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
  288. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
  289. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
  290. /*
  291. * I2C
  292. */
  293. #define CONFIG_SYS_I2C
  294. #define CONFIG_SYS_I2C_FSL
  295. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  296. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  297. #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
  298. #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
  299. #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
  300. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
  301. #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
  302. #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
  303. #define CONFIG_SYS_FSL_I2C_SPEED 100000
  304. #define CONFIG_SYS_FSL_I2C2_SPEED 100000
  305. #define CONFIG_SYS_FSL_I2C3_SPEED 100000
  306. #define CONFIG_SYS_FSL_I2C4_SPEED 100000
  307. #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
  308. #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
  309. #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
  310. #define I2C_MUX_CH_DEFAULT 0x8
  311. #define I2C_MUX_CH_VOL_MONITOR 0xa
  312. #define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv"
  313. #ifndef CONFIG_SPL_BUILD
  314. #define CONFIG_VID
  315. #endif
  316. #define CONFIG_VOL_MONITOR_IR36021_SET
  317. #define CONFIG_VOL_MONITOR_IR36021_READ
  318. /* The lowest and highest voltage allowed for T208xRDB */
  319. #define VDD_MV_MIN 819
  320. #define VDD_MV_MAX 1212
  321. /*
  322. * RapidIO
  323. */
  324. #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
  325. #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
  326. #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
  327. #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
  328. #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
  329. #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
  330. /*
  331. * for slave u-boot IMAGE instored in master memory space,
  332. * PHYS must be aligned based on the SIZE
  333. */
  334. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
  335. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
  336. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
  337. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
  338. /*
  339. * for slave UCODE and ENV instored in master memory space,
  340. * PHYS must be aligned based on the SIZE
  341. */
  342. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
  343. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
  344. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
  345. /* slave core release by master*/
  346. #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
  347. #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
  348. /*
  349. * SRIO_PCIE_BOOT - SLAVE
  350. */
  351. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  352. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
  353. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
  354. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
  355. #endif
  356. /*
  357. * eSPI - Enhanced SPI
  358. */
  359. /*
  360. * General PCI
  361. * Memory space is mapped 1-1, but I/O space must start from 0.
  362. */
  363. #define CONFIG_PCIE1 /* PCIE controller 1 */
  364. #define CONFIG_PCIE2 /* PCIE controller 2 */
  365. #define CONFIG_PCIE3 /* PCIE controller 3 */
  366. #define CONFIG_PCIE4 /* PCIE controller 4 */
  367. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  368. /* controller 1, direct to uli, tgtid 3, Base address 20000 */
  369. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  370. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  371. #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  372. #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  373. /* controller 2, Slot 2, tgtid 2, Base address 201000 */
  374. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  375. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  376. #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
  377. #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
  378. /* controller 3, Slot 1, tgtid 1, Base address 202000 */
  379. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
  380. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
  381. #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
  382. #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
  383. /* controller 4, Base address 203000 */
  384. #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
  385. #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
  386. #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
  387. #ifdef CONFIG_PCI
  388. #if !defined(CONFIG_DM_PCI)
  389. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  390. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  391. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  392. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  393. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  394. #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
  395. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
  396. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  397. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  398. #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  399. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
  400. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  401. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  402. #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
  403. #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
  404. #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
  405. #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
  406. #define CONFIG_PCI_INDIRECT_BRIDGE
  407. #endif
  408. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  409. #endif
  410. /* Qman/Bman */
  411. #ifndef CONFIG_NOBQFMAN
  412. #define CONFIG_SYS_BMAN_NUM_PORTALS 18
  413. #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  414. #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  415. #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
  416. #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
  417. #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
  418. #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
  419. #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  420. #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
  421. CONFIG_SYS_BMAN_CENA_SIZE)
  422. #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  423. #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
  424. #define CONFIG_SYS_QMAN_NUM_PORTALS 18
  425. #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
  426. #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
  427. #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
  428. #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
  429. #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
  430. #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
  431. #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  432. #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
  433. CONFIG_SYS_QMAN_CENA_SIZE)
  434. #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  435. #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
  436. #define CONFIG_SYS_DPAA_FMAN
  437. #define CONFIG_SYS_DPAA_PME
  438. #define CONFIG_SYS_PMAN
  439. #define CONFIG_SYS_DPAA_DCE
  440. #define CONFIG_SYS_DPAA_RMAN /* RMan */
  441. #define CONFIG_SYS_INTERLAKEN
  442. /* Default address of microcode for the Linux Fman driver */
  443. #if defined(CONFIG_SPIFLASH)
  444. /*
  445. * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  446. * env, so we got 0x110000.
  447. */
  448. #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
  449. #define CONFIG_CORTINA_FW_ADDR 0x120000
  450. #elif defined(CONFIG_SDCARD)
  451. /*
  452. * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  453. * about 1MB (2048 blocks), Env is stored after the image, and the env size is
  454. * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
  455. */
  456. #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
  457. #define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0)
  458. #elif defined(CONFIG_MTD_RAW_NAND)
  459. #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
  460. #define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
  461. #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  462. /*
  463. * Slave has no ucode locally, it can fetch this from remote. When implementing
  464. * in two corenet boards, slave's ucode could be stored in master's memory
  465. * space, the address can be mapped from slave TLB->slave LAW->
  466. * slave SRIO or PCIE outbound window->master inbound window->
  467. * master LAW->the ucode address in master's memory space.
  468. */
  469. #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
  470. #define CONFIG_CORTINA_FW_ADDR 0xFFE10000
  471. #else
  472. #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
  473. #define CONFIG_CORTINA_FW_ADDR 0xEFE00000
  474. #endif
  475. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  476. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  477. #endif /* CONFIG_NOBQFMAN */
  478. #ifdef CONFIG_SYS_DPAA_FMAN
  479. #define CONFIG_PHY_REALTEK
  480. #define CONFIG_CORTINA_FW_LENGTH 0x40000
  481. #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */
  482. #define RGMII_PHY2_ADDR 0x02
  483. #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */
  484. #define CORTINA_PHY_ADDR2 0x0d
  485. #define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */
  486. #define FM1_10GEC4_PHY_ADDR 0x01
  487. #endif
  488. #ifdef CONFIG_FMAN_ENET
  489. #define CONFIG_ETHPRIME "FM1@DTSEC3"
  490. #endif
  491. /*
  492. * SATA
  493. */
  494. #ifdef CONFIG_FSL_SATA_V2
  495. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  496. #define CONFIG_SATA1
  497. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  498. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  499. #define CONFIG_SATA2
  500. #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  501. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  502. #define CONFIG_LBA48
  503. #endif
  504. /*
  505. * USB
  506. */
  507. #ifdef CONFIG_USB_EHCI_HCD
  508. #define CONFIG_USB_EHCI_FSL
  509. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  510. #define CONFIG_HAS_FSL_DR_USB
  511. #endif
  512. /*
  513. * SDHC
  514. */
  515. #ifdef CONFIG_MMC
  516. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  517. #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
  518. #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
  519. #endif
  520. /*
  521. * Dynamic MTD Partition support with mtdparts
  522. */
  523. /*
  524. * Environment
  525. */
  526. /*
  527. * Miscellaneous configurable options
  528. */
  529. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  530. /*
  531. * For booting Linux, the board info and command line data
  532. * have to be in the first 64 MB of memory, since this is
  533. * the maximum mapped by the Linux kernel during initialization.
  534. */
  535. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
  536. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  537. #ifdef CONFIG_CMD_KGDB
  538. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  539. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  540. #endif
  541. /*
  542. * Environment Configuration
  543. */
  544. #define CONFIG_ROOTPATH "/opt/nfsroot"
  545. #define CONFIG_BOOTFILE "uImage"
  546. #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
  547. /* default location for tftp and bootm */
  548. #define CONFIG_LOADADDR 1000000
  549. #define __USB_PHY_TYPE utmi
  550. #define CONFIG_EXTRA_ENV_SETTINGS \
  551. "hwconfig=fsl_ddr:" \
  552. "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
  553. "bank_intlv=auto;" \
  554. "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
  555. "netdev=eth0\0" \
  556. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  557. "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  558. "tftpflash=tftpboot $loadaddr $uboot && " \
  559. "protect off $ubootaddr +$filesize && " \
  560. "erase $ubootaddr +$filesize && " \
  561. "cp.b $loadaddr $ubootaddr $filesize && " \
  562. "protect on $ubootaddr +$filesize && " \
  563. "cmp.b $loadaddr $ubootaddr $filesize\0" \
  564. "consoledev=ttyS0\0" \
  565. "ramdiskaddr=2000000\0" \
  566. "ramdiskfile=t2080rdb/ramdisk.uboot\0" \
  567. "fdtaddr=1e00000\0" \
  568. "fdtfile=t2080rdb/t2080rdb.dtb\0" \
  569. "bdev=sda3\0"
  570. /*
  571. * For emulation this causes u-boot to jump to the start of the
  572. * proof point app code automatically
  573. */
  574. #define CONFIG_PROOF_POINTS \
  575. "setenv bootargs root=/dev/$bdev rw " \
  576. "console=$consoledev,$baudrate $othbootargs;" \
  577. "cpu 1 release 0x29000000 - - -;" \
  578. "cpu 2 release 0x29000000 - - -;" \
  579. "cpu 3 release 0x29000000 - - -;" \
  580. "cpu 4 release 0x29000000 - - -;" \
  581. "cpu 5 release 0x29000000 - - -;" \
  582. "cpu 6 release 0x29000000 - - -;" \
  583. "cpu 7 release 0x29000000 - - -;" \
  584. "go 0x29000000"
  585. #define CONFIG_HVBOOT \
  586. "setenv bootargs config-addr=0x60000000; " \
  587. "bootm 0x01000000 - 0x00f00000"
  588. #define CONFIG_ALU \
  589. "setenv bootargs root=/dev/$bdev rw " \
  590. "console=$consoledev,$baudrate $othbootargs;" \
  591. "cpu 1 release 0x01000000 - - -;" \
  592. "cpu 2 release 0x01000000 - - -;" \
  593. "cpu 3 release 0x01000000 - - -;" \
  594. "cpu 4 release 0x01000000 - - -;" \
  595. "cpu 5 release 0x01000000 - - -;" \
  596. "cpu 6 release 0x01000000 - - -;" \
  597. "cpu 7 release 0x01000000 - - -;" \
  598. "go 0x01000000"
  599. #define CONFIG_LINUX \
  600. "setenv bootargs root=/dev/ram rw " \
  601. "console=$consoledev,$baudrate $othbootargs;" \
  602. "setenv ramdiskaddr 0x02000000;" \
  603. "setenv fdtaddr 0x00c00000;" \
  604. "setenv loadaddr 0x1000000;" \
  605. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  606. #define CONFIG_HDBOOT \
  607. "setenv bootargs root=/dev/$bdev rw " \
  608. "console=$consoledev,$baudrate $othbootargs;" \
  609. "tftp $loadaddr $bootfile;" \
  610. "tftp $fdtaddr $fdtfile;" \
  611. "bootm $loadaddr - $fdtaddr"
  612. #define CONFIG_NFSBOOTCOMMAND \
  613. "setenv bootargs root=/dev/nfs rw " \
  614. "nfsroot=$serverip:$rootpath " \
  615. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  616. "console=$consoledev,$baudrate $othbootargs;" \
  617. "tftp $loadaddr $bootfile;" \
  618. "tftp $fdtaddr $fdtfile;" \
  619. "bootm $loadaddr - $fdtaddr"
  620. #define CONFIG_RAMBOOTCOMMAND \
  621. "setenv bootargs root=/dev/ram rw " \
  622. "console=$consoledev,$baudrate $othbootargs;" \
  623. "tftp $ramdiskaddr $ramdiskfile;" \
  624. "tftp $loadaddr $bootfile;" \
  625. "tftp $fdtaddr $fdtfile;" \
  626. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  627. #define CONFIG_BOOTCOMMAND CONFIG_LINUX
  628. #include <asm/fsl_secure_boot.h>
  629. #endif /* __T2080RDB_H */