T208xQDS.h 26 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2011-2013 Freescale Semiconductor, Inc.
  4. */
  5. /*
  6. * T2080/T2081 QDS board configuration file
  7. */
  8. #ifndef __T208xQDS_H
  9. #define __T208xQDS_H
  10. #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
  11. #if defined(CONFIG_ARCH_T2080)
  12. #define CONFIG_FSL_SATA_V2
  13. #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */
  14. #define CONFIG_SRIO1 /* SRIO port 1 */
  15. #define CONFIG_SRIO2 /* SRIO port 2 */
  16. #elif defined(CONFIG_ARCH_T2081)
  17. #endif
  18. /* High Level Configuration Options */
  19. #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  20. #define CONFIG_ENABLE_36BIT_PHYS
  21. #ifdef CONFIG_PHYS_64BIT
  22. #define CONFIG_ADDR_MAP 1
  23. #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
  24. #endif
  25. #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  26. #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  27. #define CONFIG_ENV_OVERWRITE
  28. #ifdef CONFIG_RAMBOOT_PBL
  29. #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
  30. #define CONFIG_SPL_FLUSH_IMAGE
  31. #define CONFIG_SPL_PAD_TO 0x40000
  32. #define CONFIG_SPL_MAX_SIZE 0x28000
  33. #define RESET_VECTOR_OFFSET 0x27FFC
  34. #define BOOT_PAGE_OFFSET 0x27000
  35. #ifdef CONFIG_SPL_BUILD
  36. #define CONFIG_SPL_SKIP_RELOCATE
  37. #define CONFIG_SPL_COMMON_INIT_DDR
  38. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  39. #endif
  40. #ifdef CONFIG_MTD_RAW_NAND
  41. #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
  42. #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
  43. #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
  44. #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
  45. #if defined(CONFIG_ARCH_T2080)
  46. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg
  47. #elif defined(CONFIG_ARCH_T2081)
  48. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_nand_rcw.cfg
  49. #endif
  50. #endif
  51. #ifdef CONFIG_SPIFLASH
  52. #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
  53. #define CONFIG_SPL_SPI_FLASH_MINIMAL
  54. #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
  55. #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
  56. #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
  57. #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
  58. #ifndef CONFIG_SPL_BUILD
  59. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  60. #endif
  61. #if defined(CONFIG_ARCH_T2080)
  62. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg
  63. #elif defined(CONFIG_ARCH_T2081)
  64. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_spi_rcw.cfg
  65. #endif
  66. #endif
  67. #ifdef CONFIG_SDCARD
  68. #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
  69. #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
  70. #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
  71. #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
  72. #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
  73. #ifndef CONFIG_SPL_BUILD
  74. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  75. #endif
  76. #if defined(CONFIG_ARCH_T2080)
  77. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg
  78. #elif defined(CONFIG_ARCH_T2081)
  79. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_sd_rcw.cfg
  80. #endif
  81. #endif
  82. #endif /* CONFIG_RAMBOOT_PBL */
  83. #define CONFIG_SRIO_PCIE_BOOT_MASTER
  84. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  85. /* Set 1M boot space */
  86. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  87. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  88. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  89. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  90. #endif
  91. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  92. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  93. #endif
  94. /*
  95. * These can be toggled for performance analysis, otherwise use default.
  96. */
  97. #define CONFIG_SYS_CACHE_STASHING
  98. #define CONFIG_BTB /* toggle branch predition */
  99. #define CONFIG_DDR_ECC
  100. #ifdef CONFIG_DDR_ECC
  101. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  102. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  103. #endif
  104. #if defined(CONFIG_SPIFLASH)
  105. #elif defined(CONFIG_SDCARD)
  106. #define CONFIG_SYS_MMC_ENV_DEV 0
  107. #endif
  108. #ifndef __ASSEMBLY__
  109. unsigned long get_board_sys_clk(void);
  110. unsigned long get_board_ddr_clk(void);
  111. #endif
  112. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
  113. #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
  114. /*
  115. * Config the L3 Cache as L3 SRAM
  116. */
  117. #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
  118. #define CONFIG_SYS_L3_SIZE (512 << 10)
  119. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
  120. #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
  121. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
  122. #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
  123. #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
  124. #define CONFIG_SYS_DCSRBAR 0xf0000000
  125. #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  126. /* EEPROM */
  127. #define CONFIG_ID_EEPROM
  128. #define CONFIG_SYS_I2C_EEPROM_NXID
  129. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  130. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  131. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  132. /*
  133. * DDR Setup
  134. */
  135. #define CONFIG_VERY_BIG_RAM
  136. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  137. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  138. #define CONFIG_DIMM_SLOTS_PER_CTLR 2
  139. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  140. #define CONFIG_DDR_SPD
  141. #define CONFIG_SYS_SPD_BUS_NUM 0
  142. #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
  143. #define SPD_EEPROM_ADDRESS1 0x51
  144. #define SPD_EEPROM_ADDRESS2 0x52
  145. #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
  146. #define CTRL_INTLV_PREFERED cacheline
  147. /*
  148. * IFC Definitions
  149. */
  150. #define CONFIG_SYS_FLASH_BASE 0xe0000000
  151. #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  152. #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
  153. #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  154. + 0x8000000) | \
  155. CSPR_PORT_SIZE_16 | \
  156. CSPR_MSEL_NOR | \
  157. CSPR_V)
  158. #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
  159. #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  160. CSPR_PORT_SIZE_16 | \
  161. CSPR_MSEL_NOR | \
  162. CSPR_V)
  163. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  164. /* NOR Flash Timing Params */
  165. #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
  166. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  167. FTIM0_NOR_TEADC(0x5) | \
  168. FTIM0_NOR_TEAHC(0x5))
  169. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  170. FTIM1_NOR_TRAD_NOR(0x1A) |\
  171. FTIM1_NOR_TSEQRAD_NOR(0x13))
  172. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  173. FTIM2_NOR_TCH(0x4) | \
  174. FTIM2_NOR_TWPH(0x0E) | \
  175. FTIM2_NOR_TWP(0x1c))
  176. #define CONFIG_SYS_NOR_FTIM3 0x0
  177. #define CONFIG_SYS_FLASH_QUIET_TEST
  178. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  179. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  180. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  181. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  182. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  183. #define CONFIG_SYS_FLASH_EMPTY_INFO
  184. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
  185. + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
  186. #define CONFIG_FSL_QIXIS /* use common QIXIS code */
  187. #define QIXIS_BASE 0xffdf0000
  188. #define QIXIS_LBMAP_SWITCH 6
  189. #define QIXIS_LBMAP_MASK 0x0f
  190. #define QIXIS_LBMAP_SHIFT 0
  191. #define QIXIS_LBMAP_DFLTBANK 0x00
  192. #define QIXIS_LBMAP_ALTBANK 0x04
  193. #define QIXIS_LBMAP_NAND 0x09
  194. #define QIXIS_LBMAP_SD 0x00
  195. #define QIXIS_RCW_SRC_NAND 0x104
  196. #define QIXIS_RCW_SRC_SD 0x040
  197. #define QIXIS_RST_CTL_RESET 0x83
  198. #define QIXIS_RST_FORCE_MEM 0x1
  199. #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  200. #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  201. #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  202. #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
  203. #define CONFIG_SYS_CSPR3_EXT (0xf)
  204. #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
  205. | CSPR_PORT_SIZE_8 \
  206. | CSPR_MSEL_GPCM \
  207. | CSPR_V)
  208. #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
  209. #define CONFIG_SYS_CSOR3 0x0
  210. /* QIXIS Timing parameters for IFC CS3 */
  211. #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  212. FTIM0_GPCM_TEADC(0x0e) | \
  213. FTIM0_GPCM_TEAHC(0x0e))
  214. #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
  215. FTIM1_GPCM_TRAD(0x3f))
  216. #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
  217. FTIM2_GPCM_TCH(0x8) | \
  218. FTIM2_GPCM_TWP(0x1f))
  219. #define CONFIG_SYS_CS3_FTIM3 0x0
  220. /* NAND Flash on IFC */
  221. #define CONFIG_NAND_FSL_IFC
  222. #define CONFIG_SYS_NAND_BASE 0xff800000
  223. #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
  224. #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
  225. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  226. | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  227. | CSPR_MSEL_NAND /* MSEL = NAND */ \
  228. | CSPR_V)
  229. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  230. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  231. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  232. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  233. | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
  234. | CSOR_NAND_PGS_2K /* Page Size = 2K */\
  235. | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
  236. | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  237. #define CONFIG_SYS_NAND_ONFI_DETECTION
  238. /* ONFI NAND Flash mode0 Timing Params */
  239. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
  240. FTIM0_NAND_TWP(0x18) | \
  241. FTIM0_NAND_TWCHT(0x07) | \
  242. FTIM0_NAND_TWH(0x0a))
  243. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  244. FTIM1_NAND_TWBE(0x39) | \
  245. FTIM1_NAND_TRR(0x0e) | \
  246. FTIM1_NAND_TRP(0x18))
  247. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  248. FTIM2_NAND_TREH(0x0a) | \
  249. FTIM2_NAND_TWHRE(0x1e))
  250. #define CONFIG_SYS_NAND_FTIM3 0x0
  251. #define CONFIG_SYS_NAND_DDR_LAW 11
  252. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  253. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  254. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  255. #if defined(CONFIG_MTD_RAW_NAND)
  256. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  257. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  258. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  259. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  260. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  261. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  262. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  263. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  264. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
  265. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
  266. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  267. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  268. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  269. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  270. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  271. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  272. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
  273. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
  274. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
  275. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
  276. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
  277. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
  278. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
  279. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
  280. #else
  281. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  282. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
  283. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  284. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  285. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  286. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  287. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  288. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  289. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
  290. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
  291. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  292. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  293. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  294. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  295. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  296. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  297. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
  298. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
  299. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
  300. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
  301. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
  302. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
  303. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
  304. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
  305. #endif
  306. #if defined(CONFIG_RAMBOOT_PBL)
  307. #define CONFIG_SYS_RAMBOOT
  308. #endif
  309. #ifdef CONFIG_SPL_BUILD
  310. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  311. #else
  312. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  313. #endif
  314. #define CONFIG_HWCONFIG
  315. /* define to use L1 as initial stack */
  316. #define CONFIG_L1_INIT_RAM
  317. #define CONFIG_SYS_INIT_RAM_LOCK
  318. #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
  319. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  320. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
  321. /* The assembler doesn't like typecast */
  322. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  323. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  324. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  325. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  326. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  327. GENERATED_GBL_DATA_SIZE)
  328. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  329. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  330. #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
  331. /*
  332. * Serial Port
  333. */
  334. #define CONFIG_SYS_NS16550_SERIAL
  335. #define CONFIG_SYS_NS16550_REG_SIZE 1
  336. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  337. #define CONFIG_SYS_BAUDRATE_TABLE \
  338. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  339. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
  340. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
  341. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
  342. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
  343. /*
  344. * I2C
  345. */
  346. #define CONFIG_SYS_I2C
  347. #define CONFIG_SYS_I2C_FSL
  348. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  349. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  350. #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
  351. #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
  352. #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
  353. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
  354. #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
  355. #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
  356. #define CONFIG_SYS_FSL_I2C_SPEED 100000
  357. #define CONFIG_SYS_FSL_I2C2_SPEED 100000
  358. #define CONFIG_SYS_FSL_I2C3_SPEED 100000
  359. #define CONFIG_SYS_FSL_I2C4_SPEED 100000
  360. #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
  361. #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
  362. #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
  363. #define I2C_MUX_CH_DEFAULT 0x8
  364. #define I2C_MUX_CH_VOL_MONITOR 0xa
  365. /* Voltage monitor on channel 2*/
  366. #define I2C_VOL_MONITOR_ADDR 0x40
  367. #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
  368. #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
  369. #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
  370. #define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv"
  371. #ifndef CONFIG_SPL_BUILD
  372. #define CONFIG_VID
  373. #endif
  374. #define CONFIG_VOL_MONITOR_IR36021_SET
  375. #define CONFIG_VOL_MONITOR_IR36021_READ
  376. /* The lowest and highest voltage allowed for T208xQDS */
  377. #define VDD_MV_MIN 819
  378. #define VDD_MV_MAX 1212
  379. /*
  380. * RapidIO
  381. */
  382. #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
  383. #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
  384. #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
  385. #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
  386. #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
  387. #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
  388. /*
  389. * for slave u-boot IMAGE instored in master memory space,
  390. * PHYS must be aligned based on the SIZE
  391. */
  392. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
  393. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
  394. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
  395. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
  396. /*
  397. * for slave UCODE and ENV instored in master memory space,
  398. * PHYS must be aligned based on the SIZE
  399. */
  400. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
  401. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
  402. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
  403. /* slave core release by master*/
  404. #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
  405. #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
  406. /*
  407. * SRIO_PCIE_BOOT - SLAVE
  408. */
  409. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  410. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
  411. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
  412. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
  413. #endif
  414. /*
  415. * eSPI - Enhanced SPI
  416. */
  417. /*
  418. * General PCI
  419. * Memory space is mapped 1-1, but I/O space must start from 0.
  420. */
  421. #define CONFIG_PCIE1 /* PCIE controller 1 */
  422. #define CONFIG_PCIE2 /* PCIE controller 2 */
  423. #define CONFIG_PCIE3 /* PCIE controller 3 */
  424. #define CONFIG_PCIE4 /* PCIE controller 4 */
  425. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  426. /* controller 1, direct to uli, tgtid 3, Base address 20000 */
  427. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  428. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  429. #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  430. #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  431. /* controller 2, Slot 2, tgtid 2, Base address 201000 */
  432. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  433. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  434. #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
  435. #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
  436. /* controller 3, Slot 1, tgtid 1, Base address 202000 */
  437. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
  438. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
  439. #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
  440. #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
  441. /* controller 4, Base address 203000 */
  442. #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
  443. #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
  444. #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
  445. #ifdef CONFIG_PCI
  446. #if !defined(CONFIG_DM_PCI)
  447. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  448. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  449. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  450. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  451. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  452. #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
  453. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
  454. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  455. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  456. #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  457. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
  458. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  459. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  460. #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
  461. #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
  462. #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
  463. #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
  464. #define CONFIG_PCI_INDIRECT_BRIDGE
  465. #endif
  466. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  467. #endif
  468. /* Qman/Bman */
  469. #ifndef CONFIG_NOBQFMAN
  470. #define CONFIG_SYS_BMAN_NUM_PORTALS 18
  471. #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  472. #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  473. #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
  474. #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
  475. #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
  476. #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
  477. #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  478. #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
  479. CONFIG_SYS_BMAN_CENA_SIZE)
  480. #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  481. #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
  482. #define CONFIG_SYS_QMAN_NUM_PORTALS 18
  483. #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
  484. #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
  485. #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
  486. #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
  487. #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
  488. #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
  489. #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  490. #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
  491. CONFIG_SYS_QMAN_CENA_SIZE)
  492. #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  493. #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
  494. #define CONFIG_SYS_DPAA_FMAN
  495. #define CONFIG_SYS_DPAA_PME
  496. #define CONFIG_SYS_PMAN
  497. #define CONFIG_SYS_DPAA_DCE
  498. #define CONFIG_SYS_DPAA_RMAN /* RMan */
  499. #define CONFIG_SYS_INTERLAKEN
  500. /* Default address of microcode for the Linux Fman driver */
  501. #if defined(CONFIG_SPIFLASH)
  502. /*
  503. * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  504. * env, so we got 0x110000.
  505. */
  506. #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
  507. #elif defined(CONFIG_SDCARD)
  508. /*
  509. * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  510. * about 1MB (2048 blocks), Env is stored after the image, and the env size is
  511. * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
  512. */
  513. #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
  514. #elif defined(CONFIG_MTD_RAW_NAND)
  515. #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
  516. #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  517. /*
  518. * Slave has no ucode locally, it can fetch this from remote. When implementing
  519. * in two corenet boards, slave's ucode could be stored in master's memory
  520. * space, the address can be mapped from slave TLB->slave LAW->
  521. * slave SRIO or PCIE outbound window->master inbound window->
  522. * master LAW->the ucode address in master's memory space.
  523. */
  524. #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
  525. #else
  526. #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
  527. #endif
  528. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  529. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  530. #endif /* CONFIG_NOBQFMAN */
  531. #ifdef CONFIG_SYS_DPAA_FMAN
  532. #define CONFIG_PHY_VITESSE
  533. #define CONFIG_PHY_REALTEK
  534. #define CONFIG_PHY_TERANETICS
  535. #define RGMII_PHY1_ADDR 0x1
  536. #define RGMII_PHY2_ADDR 0x2
  537. #define FM1_10GEC1_PHY_ADDR 0x3
  538. #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  539. #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
  540. #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  541. #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  542. #endif
  543. #ifdef CONFIG_FMAN_ENET
  544. #define CONFIG_ETHPRIME "FM1@DTSEC3"
  545. #endif
  546. /*
  547. * SATA
  548. */
  549. #ifdef CONFIG_FSL_SATA_V2
  550. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  551. #define CONFIG_SATA1
  552. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  553. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  554. #define CONFIG_SATA2
  555. #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  556. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  557. #define CONFIG_LBA48
  558. #endif
  559. /*
  560. * USB
  561. */
  562. #ifdef CONFIG_USB_EHCI_HCD
  563. #define CONFIG_USB_EHCI_FSL
  564. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  565. #define CONFIG_HAS_FSL_DR_USB
  566. #endif
  567. /*
  568. * SDHC
  569. */
  570. #ifdef CONFIG_MMC
  571. #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
  572. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  573. #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
  574. #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
  575. #define CONFIG_FSL_ESDHC_ADAPTER_IDENT
  576. #endif
  577. /*
  578. * Dynamic MTD Partition support with mtdparts
  579. */
  580. /*
  581. * Environment
  582. */
  583. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  584. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  585. /*
  586. * Miscellaneous configurable options
  587. */
  588. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  589. /*
  590. * For booting Linux, the board info and command line data
  591. * have to be in the first 64 MB of memory, since this is
  592. * the maximum mapped by the Linux kernel during initialization.
  593. */
  594. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
  595. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  596. #ifdef CONFIG_CMD_KGDB
  597. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  598. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  599. #endif
  600. /*
  601. * Environment Configuration
  602. */
  603. #define CONFIG_ROOTPATH "/opt/nfsroot"
  604. #define CONFIG_BOOTFILE "uImage"
  605. #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
  606. /* default location for tftp and bootm */
  607. #define CONFIG_LOADADDR 1000000
  608. #define __USB_PHY_TYPE utmi
  609. #define CONFIG_EXTRA_ENV_SETTINGS \
  610. "hwconfig=fsl_ddr:" \
  611. "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
  612. "bank_intlv=auto;" \
  613. "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
  614. "netdev=eth0\0" \
  615. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  616. "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  617. "tftpflash=tftpboot $loadaddr $uboot && " \
  618. "protect off $ubootaddr +$filesize && " \
  619. "erase $ubootaddr +$filesize && " \
  620. "cp.b $loadaddr $ubootaddr $filesize && " \
  621. "protect on $ubootaddr +$filesize && " \
  622. "cmp.b $loadaddr $ubootaddr $filesize\0" \
  623. "consoledev=ttyS0\0" \
  624. "ramdiskaddr=2000000\0" \
  625. "ramdiskfile=t2080qds/ramdisk.uboot\0" \
  626. "fdtaddr=1e00000\0" \
  627. "fdtfile=t2080qds/t2080qds.dtb\0" \
  628. "bdev=sda3\0"
  629. /*
  630. * For emulation this causes u-boot to jump to the start of the
  631. * proof point app code automatically
  632. */
  633. #define CONFIG_PROOF_POINTS \
  634. "setenv bootargs root=/dev/$bdev rw " \
  635. "console=$consoledev,$baudrate $othbootargs;" \
  636. "cpu 1 release 0x29000000 - - -;" \
  637. "cpu 2 release 0x29000000 - - -;" \
  638. "cpu 3 release 0x29000000 - - -;" \
  639. "cpu 4 release 0x29000000 - - -;" \
  640. "cpu 5 release 0x29000000 - - -;" \
  641. "cpu 6 release 0x29000000 - - -;" \
  642. "cpu 7 release 0x29000000 - - -;" \
  643. "go 0x29000000"
  644. #define CONFIG_HVBOOT \
  645. "setenv bootargs config-addr=0x60000000; " \
  646. "bootm 0x01000000 - 0x00f00000"
  647. #define CONFIG_ALU \
  648. "setenv bootargs root=/dev/$bdev rw " \
  649. "console=$consoledev,$baudrate $othbootargs;" \
  650. "cpu 1 release 0x01000000 - - -;" \
  651. "cpu 2 release 0x01000000 - - -;" \
  652. "cpu 3 release 0x01000000 - - -;" \
  653. "cpu 4 release 0x01000000 - - -;" \
  654. "cpu 5 release 0x01000000 - - -;" \
  655. "cpu 6 release 0x01000000 - - -;" \
  656. "cpu 7 release 0x01000000 - - -;" \
  657. "go 0x01000000"
  658. #define CONFIG_LINUX \
  659. "setenv bootargs root=/dev/ram rw " \
  660. "console=$consoledev,$baudrate $othbootargs;" \
  661. "setenv ramdiskaddr 0x02000000;" \
  662. "setenv fdtaddr 0x00c00000;" \
  663. "setenv loadaddr 0x1000000;" \
  664. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  665. #define CONFIG_HDBOOT \
  666. "setenv bootargs root=/dev/$bdev rw " \
  667. "console=$consoledev,$baudrate $othbootargs;" \
  668. "tftp $loadaddr $bootfile;" \
  669. "tftp $fdtaddr $fdtfile;" \
  670. "bootm $loadaddr - $fdtaddr"
  671. #define CONFIG_NFSBOOTCOMMAND \
  672. "setenv bootargs root=/dev/nfs rw " \
  673. "nfsroot=$serverip:$rootpath " \
  674. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  675. "console=$consoledev,$baudrate $othbootargs;" \
  676. "tftp $loadaddr $bootfile;" \
  677. "tftp $fdtaddr $fdtfile;" \
  678. "bootm $loadaddr - $fdtaddr"
  679. #define CONFIG_RAMBOOTCOMMAND \
  680. "setenv bootargs root=/dev/ram rw " \
  681. "console=$consoledev,$baudrate $othbootargs;" \
  682. "tftp $ramdiskaddr $ramdiskfile;" \
  683. "tftp $loadaddr $bootfile;" \
  684. "tftp $fdtaddr $fdtfile;" \
  685. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  686. #define CONFIG_BOOTCOMMAND CONFIG_LINUX
  687. #include <asm/fsl_secure_boot.h>
  688. #endif /* __T208xQDS_H */