T102xRDB.h 24 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. */
  5. /*
  6. * T1024/T1023 RDB board configuration file
  7. */
  8. #ifndef __T1024RDB_H
  9. #define __T1024RDB_H
  10. /* High Level Configuration Options */
  11. #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  12. #define CONFIG_ENABLE_36BIT_PHYS
  13. #ifdef CONFIG_PHYS_64BIT
  14. #define CONFIG_ADDR_MAP 1
  15. #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
  16. #endif
  17. #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  18. #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  19. #define CONFIG_ENV_OVERWRITE
  20. /* support deep sleep */
  21. #ifdef CONFIG_ARCH_T1024
  22. #define CONFIG_DEEP_SLEEP
  23. #endif
  24. #ifdef CONFIG_RAMBOOT_PBL
  25. #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
  26. #define CONFIG_SPL_FLUSH_IMAGE
  27. #define CONFIG_SPL_PAD_TO 0x40000
  28. #define CONFIG_SPL_MAX_SIZE 0x28000
  29. #define RESET_VECTOR_OFFSET 0x27FFC
  30. #define BOOT_PAGE_OFFSET 0x27000
  31. #ifdef CONFIG_SPL_BUILD
  32. #define CONFIG_SPL_SKIP_RELOCATE
  33. #define CONFIG_SPL_COMMON_INIT_DDR
  34. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  35. #endif
  36. #ifdef CONFIG_MTD_RAW_NAND
  37. #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
  38. #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
  39. #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
  40. #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
  41. #if defined(CONFIG_TARGET_T1024RDB)
  42. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg
  43. #elif defined(CONFIG_TARGET_T1023RDB)
  44. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg
  45. #endif
  46. #endif
  47. #ifdef CONFIG_SPIFLASH
  48. #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
  49. #define CONFIG_SPL_SPI_FLASH_MINIMAL
  50. #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
  51. #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
  52. #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
  53. #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
  54. #ifndef CONFIG_SPL_BUILD
  55. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  56. #endif
  57. #if defined(CONFIG_TARGET_T1024RDB)
  58. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg
  59. #elif defined(CONFIG_TARGET_T1023RDB)
  60. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg
  61. #endif
  62. #endif
  63. #ifdef CONFIG_SDCARD
  64. #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
  65. #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
  66. #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
  67. #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
  68. #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
  69. #ifndef CONFIG_SPL_BUILD
  70. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  71. #endif
  72. #if defined(CONFIG_TARGET_T1024RDB)
  73. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg
  74. #elif defined(CONFIG_TARGET_T1023RDB)
  75. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg
  76. #endif
  77. #endif
  78. #endif /* CONFIG_RAMBOOT_PBL */
  79. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  80. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  81. #endif
  82. /* PCIe Boot - Master */
  83. #define CONFIG_SRIO_PCIE_BOOT_MASTER
  84. /*
  85. * for slave u-boot IMAGE instored in master memory space,
  86. * PHYS must be aligned based on the SIZE
  87. */
  88. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
  89. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
  90. #ifdef CONFIG_PHYS_64BIT
  91. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
  92. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
  93. #else
  94. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
  95. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
  96. #endif
  97. /*
  98. * for slave UCODE and ENV instored in master memory space,
  99. * PHYS must be aligned based on the SIZE
  100. */
  101. #ifdef CONFIG_PHYS_64BIT
  102. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
  103. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
  104. #else
  105. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
  106. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
  107. #endif
  108. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
  109. /* slave core release by master*/
  110. #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
  111. #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
  112. /* PCIe Boot - Slave */
  113. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  114. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
  115. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
  116. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
  117. /* Set 1M boot space for PCIe boot */
  118. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  119. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  120. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  121. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  122. #endif
  123. #if defined(CONFIG_SPIFLASH)
  124. #elif defined(CONFIG_SDCARD)
  125. #define CONFIG_SYS_MMC_ENV_DEV 0
  126. #endif
  127. #ifndef __ASSEMBLY__
  128. unsigned long get_board_sys_clk(void);
  129. unsigned long get_board_ddr_clk(void);
  130. #endif
  131. #define CONFIG_SYS_CLK_FREQ 100000000
  132. #define CONFIG_DDR_CLK_FREQ 100000000
  133. /*
  134. * These can be toggled for performance analysis, otherwise use default.
  135. */
  136. #define CONFIG_SYS_CACHE_STASHING
  137. #define CONFIG_BACKSIDE_L2_CACHE
  138. #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
  139. #define CONFIG_BTB /* toggle branch predition */
  140. #define CONFIG_DDR_ECC
  141. #ifdef CONFIG_DDR_ECC
  142. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  143. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  144. #endif
  145. #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
  146. #define CONFIG_SYS_MEMTEST_END 0x00400000
  147. /*
  148. * Config the L3 Cache as L3 SRAM
  149. */
  150. #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
  151. #define CONFIG_SYS_L3_SIZE (256 << 10)
  152. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
  153. #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
  154. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
  155. #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
  156. #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
  157. #ifdef CONFIG_PHYS_64BIT
  158. #define CONFIG_SYS_DCSRBAR 0xf0000000
  159. #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  160. #endif
  161. /* EEPROM */
  162. #define CONFIG_ID_EEPROM
  163. #define CONFIG_SYS_I2C_EEPROM_NXID
  164. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  165. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
  166. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  167. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  168. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  169. /*
  170. * DDR Setup
  171. */
  172. #define CONFIG_VERY_BIG_RAM
  173. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  174. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  175. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  176. #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
  177. #if defined(CONFIG_TARGET_T1024RDB)
  178. #define CONFIG_DDR_SPD
  179. #define CONFIG_SYS_SPD_BUS_NUM 0
  180. #define SPD_EEPROM_ADDRESS 0x51
  181. #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
  182. #elif defined(CONFIG_TARGET_T1023RDB)
  183. #define CONFIG_SYS_DDR_RAW_TIMING
  184. #define CONFIG_SYS_SDRAM_SIZE 2048
  185. #endif
  186. /*
  187. * IFC Definitions
  188. */
  189. #define CONFIG_SYS_FLASH_BASE 0xe8000000
  190. #ifdef CONFIG_PHYS_64BIT
  191. #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  192. #else
  193. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  194. #endif
  195. #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
  196. #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  197. CSPR_PORT_SIZE_16 | \
  198. CSPR_MSEL_NOR | \
  199. CSPR_V)
  200. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  201. /* NOR Flash Timing Params */
  202. #if defined(CONFIG_TARGET_T1024RDB)
  203. #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
  204. #elif defined(CONFIG_TARGET_T1023RDB)
  205. #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \
  206. CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
  207. #endif
  208. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  209. FTIM0_NOR_TEADC(0x5) | \
  210. FTIM0_NOR_TEAHC(0x5))
  211. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  212. FTIM1_NOR_TRAD_NOR(0x1A) |\
  213. FTIM1_NOR_TSEQRAD_NOR(0x13))
  214. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  215. FTIM2_NOR_TCH(0x4) | \
  216. FTIM2_NOR_TWPH(0x0E) | \
  217. FTIM2_NOR_TWP(0x1c))
  218. #define CONFIG_SYS_NOR_FTIM3 0x0
  219. #define CONFIG_SYS_FLASH_QUIET_TEST
  220. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  221. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  222. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  223. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  224. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  225. #define CONFIG_SYS_FLASH_EMPTY_INFO
  226. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
  227. #ifdef CONFIG_TARGET_T1024RDB
  228. /* CPLD on IFC */
  229. #define CONFIG_SYS_CPLD_BASE 0xffdf0000
  230. #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
  231. #define CONFIG_SYS_CSPR2_EXT (0xf)
  232. #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
  233. | CSPR_PORT_SIZE_8 \
  234. | CSPR_MSEL_GPCM \
  235. | CSPR_V)
  236. #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
  237. #define CONFIG_SYS_CSOR2 0x0
  238. /* CPLD Timing parameters for IFC CS2 */
  239. #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  240. FTIM0_GPCM_TEADC(0x0e) | \
  241. FTIM0_GPCM_TEAHC(0x0e))
  242. #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
  243. FTIM1_GPCM_TRAD(0x1f))
  244. #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
  245. FTIM2_GPCM_TCH(0x8) | \
  246. FTIM2_GPCM_TWP(0x1f))
  247. #define CONFIG_SYS_CS2_FTIM3 0x0
  248. #endif
  249. /* NAND Flash on IFC */
  250. #define CONFIG_NAND_FSL_IFC
  251. #define CONFIG_SYS_NAND_BASE 0xff800000
  252. #ifdef CONFIG_PHYS_64BIT
  253. #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
  254. #else
  255. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  256. #endif
  257. #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
  258. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  259. | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  260. | CSPR_MSEL_NAND /* MSEL = NAND */ \
  261. | CSPR_V)
  262. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  263. #if defined(CONFIG_TARGET_T1024RDB)
  264. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  265. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  266. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  267. | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
  268. | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
  269. | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
  270. | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  271. #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
  272. #elif defined(CONFIG_TARGET_T1023RDB)
  273. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  274. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  275. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  276. | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \
  277. | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
  278. | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \
  279. | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  280. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  281. #endif
  282. #define CONFIG_SYS_NAND_ONFI_DETECTION
  283. /* ONFI NAND Flash mode0 Timing Params */
  284. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
  285. FTIM0_NAND_TWP(0x18) | \
  286. FTIM0_NAND_TWCHT(0x07) | \
  287. FTIM0_NAND_TWH(0x0a))
  288. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  289. FTIM1_NAND_TWBE(0x39) | \
  290. FTIM1_NAND_TRR(0x0e) | \
  291. FTIM1_NAND_TRP(0x18))
  292. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  293. FTIM2_NAND_TREH(0x0a) | \
  294. FTIM2_NAND_TWHRE(0x1e))
  295. #define CONFIG_SYS_NAND_FTIM3 0x0
  296. #define CONFIG_SYS_NAND_DDR_LAW 11
  297. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  298. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  299. #if defined(CONFIG_MTD_RAW_NAND)
  300. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  301. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  302. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  303. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  304. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  305. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  306. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  307. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  308. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
  309. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
  310. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  311. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  312. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  313. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  314. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  315. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  316. #else
  317. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  318. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
  319. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  320. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  321. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  322. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  323. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  324. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  325. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
  326. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
  327. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
  328. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
  329. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
  330. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
  331. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
  332. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
  333. #endif
  334. #ifdef CONFIG_SPL_BUILD
  335. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  336. #else
  337. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  338. #endif
  339. #if defined(CONFIG_RAMBOOT_PBL)
  340. #define CONFIG_SYS_RAMBOOT
  341. #endif
  342. #define CONFIG_HWCONFIG
  343. /* define to use L1 as initial stack */
  344. #define CONFIG_L1_INIT_RAM
  345. #define CONFIG_SYS_INIT_RAM_LOCK
  346. #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
  347. #ifdef CONFIG_PHYS_64BIT
  348. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  349. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
  350. /* The assembler doesn't like typecast */
  351. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  352. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  353. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  354. #else
  355. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
  356. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
  357. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
  358. #endif
  359. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  360. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  361. GENERATED_GBL_DATA_SIZE)
  362. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  363. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  364. #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
  365. /* Serial Port */
  366. #define CONFIG_SYS_NS16550_SERIAL
  367. #define CONFIG_SYS_NS16550_REG_SIZE 1
  368. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  369. #define CONFIG_SYS_BAUDRATE_TABLE \
  370. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  371. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
  372. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
  373. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
  374. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
  375. /* Video */
  376. #undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */
  377. #ifdef CONFIG_FSL_DIU_FB
  378. #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
  379. #define CONFIG_VIDEO_LOGO
  380. #define CONFIG_VIDEO_BMP_LOGO
  381. #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
  382. /*
  383. * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
  384. * disable empty flash sector detection, which is I/O-intensive.
  385. */
  386. #undef CONFIG_SYS_FLASH_EMPTY_INFO
  387. #endif
  388. /* I2C */
  389. #define CONFIG_SYS_I2C
  390. #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
  391. #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
  392. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  393. #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */
  394. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  395. #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
  396. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
  397. #define I2C_PCA6408_BUS_NUM 1
  398. #define I2C_PCA6408_ADDR 0x20
  399. /* I2C bus multiplexer */
  400. #define I2C_MUX_CH_DEFAULT 0x8
  401. /*
  402. * RTC configuration
  403. */
  404. #define RTC
  405. #define CONFIG_RTC_DS1337 1
  406. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  407. /*
  408. * eSPI - Enhanced SPI
  409. */
  410. /*
  411. * General PCIe
  412. * Memory space is mapped 1-1, but I/O space must start from 0.
  413. */
  414. #define CONFIG_PCIE1 /* PCIE controller 1 */
  415. #define CONFIG_PCIE2 /* PCIE controller 2 */
  416. #define CONFIG_PCIE3 /* PCIE controller 3 */
  417. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  418. #ifdef CONFIG_PCI
  419. /* controller 1, direct to uli, tgtid 3, Base address 20000 */
  420. #ifdef CONFIG_PCIE1
  421. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  422. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  423. #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  424. #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  425. #endif
  426. /* controller 2, Slot 2, tgtid 2, Base address 201000 */
  427. #ifdef CONFIG_PCIE2
  428. #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
  429. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
  430. #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
  431. #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
  432. #endif
  433. /* controller 3, Slot 1, tgtid 1, Base address 202000 */
  434. #ifdef CONFIG_PCIE3
  435. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
  436. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
  437. #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
  438. #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
  439. #endif
  440. #if !defined(CONFIG_DM_PCI)
  441. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  442. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  443. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
  444. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  445. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  446. #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
  447. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
  448. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  449. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  450. #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  451. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
  452. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  453. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  454. #define CONFIG_PCI_INDIRECT_BRIDGE
  455. #endif
  456. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  457. #endif /* CONFIG_PCI */
  458. /*
  459. * USB
  460. */
  461. #define CONFIG_HAS_FSL_DR_USB
  462. #ifdef CONFIG_HAS_FSL_DR_USB
  463. #define CONFIG_USB_EHCI_FSL
  464. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  465. #endif
  466. /*
  467. * SDHC
  468. */
  469. #ifdef CONFIG_MMC
  470. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  471. #endif
  472. /* Qman/Bman */
  473. #ifndef CONFIG_NOBQFMAN
  474. #define CONFIG_SYS_BMAN_NUM_PORTALS 10
  475. #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  476. #ifdef CONFIG_PHYS_64BIT
  477. #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  478. #else
  479. #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
  480. #endif
  481. #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
  482. #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
  483. #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
  484. #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
  485. #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  486. #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
  487. CONFIG_SYS_BMAN_CENA_SIZE)
  488. #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  489. #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
  490. #define CONFIG_SYS_QMAN_NUM_PORTALS 10
  491. #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
  492. #ifdef CONFIG_PHYS_64BIT
  493. #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
  494. #else
  495. #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
  496. #endif
  497. #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
  498. #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
  499. #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
  500. #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
  501. #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  502. #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
  503. CONFIG_SYS_QMAN_CENA_SIZE)
  504. #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  505. #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
  506. #define CONFIG_SYS_DPAA_FMAN
  507. /* Default address of microcode for the Linux FMan driver */
  508. #if defined(CONFIG_SPIFLASH)
  509. /*
  510. * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  511. * env, so we got 0x110000.
  512. */
  513. #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
  514. #define CONFIG_SYS_QE_FW_ADDR 0x130000
  515. #elif defined(CONFIG_SDCARD)
  516. /*
  517. * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  518. * about 1MB (2048 blocks), Env is stored after the image, and the env size is
  519. * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
  520. */
  521. #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
  522. #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
  523. #elif defined(CONFIG_MTD_RAW_NAND)
  524. #if defined(CONFIG_TARGET_T1024RDB)
  525. #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
  526. #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
  527. #elif defined(CONFIG_TARGET_T1023RDB)
  528. #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
  529. #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
  530. #endif
  531. #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  532. /*
  533. * Slave has no ucode locally, it can fetch this from remote. When implementing
  534. * in two corenet boards, slave's ucode could be stored in master's memory
  535. * space, the address can be mapped from slave TLB->slave LAW->
  536. * slave SRIO or PCIE outbound window->master inbound window->
  537. * master LAW->the ucode address in master's memory space.
  538. */
  539. #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
  540. #else
  541. #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
  542. #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
  543. #endif
  544. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  545. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  546. #endif /* CONFIG_NOBQFMAN */
  547. #ifdef CONFIG_SYS_DPAA_FMAN
  548. #define CONFIG_PHY_REALTEK
  549. #if defined(CONFIG_TARGET_T1024RDB)
  550. #define RGMII_PHY1_ADDR 0x2
  551. #define RGMII_PHY2_ADDR 0x6
  552. #define SGMII_AQR_PHY_ADDR 0x2
  553. #define FM1_10GEC1_PHY_ADDR 0x1
  554. #elif defined(CONFIG_TARGET_T1023RDB)
  555. #define RGMII_PHY1_ADDR 0x1
  556. #define SGMII_RTK_PHY_ADDR 0x3
  557. #define SGMII_AQR_PHY_ADDR 0x2
  558. #endif
  559. #endif
  560. #ifdef CONFIG_FMAN_ENET
  561. #define CONFIG_ETHPRIME "FM1@DTSEC4"
  562. #endif
  563. /*
  564. * Dynamic MTD Partition support with mtdparts
  565. */
  566. /*
  567. * Environment
  568. */
  569. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  570. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  571. /*
  572. * Miscellaneous configurable options
  573. */
  574. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  575. /*
  576. * For booting Linux, the board info and command line data
  577. * have to be in the first 64 MB of memory, since this is
  578. * the maximum mapped by the Linux kernel during initialization.
  579. */
  580. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
  581. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  582. #ifdef CONFIG_CMD_KGDB
  583. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  584. #endif
  585. /*
  586. * Environment Configuration
  587. */
  588. #define CONFIG_ROOTPATH "/opt/nfsroot"
  589. #define CONFIG_BOOTFILE "uImage"
  590. #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
  591. #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */
  592. #define __USB_PHY_TYPE utmi
  593. #ifdef CONFIG_ARCH_T1024
  594. #define CONFIG_BOARDNAME t1024rdb
  595. #define BANK_INTLV cs0_cs1
  596. #else
  597. #define CONFIG_BOARDNAME t1023rdb
  598. #define BANK_INTLV null
  599. #endif
  600. #define CONFIG_EXTRA_ENV_SETTINGS \
  601. "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
  602. "bank_intlv=" __stringify(BANK_INTLV) "\0" \
  603. "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
  604. "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
  605. "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \
  606. __stringify(CONFIG_BOARDNAME) ".dtb\0" \
  607. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  608. "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  609. "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
  610. "netdev=eth0\0" \
  611. "tftpflash=tftpboot $loadaddr $uboot && " \
  612. "protect off $ubootaddr +$filesize && " \
  613. "erase $ubootaddr +$filesize && " \
  614. "cp.b $loadaddr $ubootaddr $filesize && " \
  615. "protect on $ubootaddr +$filesize && " \
  616. "cmp.b $loadaddr $ubootaddr $filesize\0" \
  617. "consoledev=ttyS0\0" \
  618. "ramdiskaddr=2000000\0" \
  619. "fdtaddr=1e00000\0" \
  620. "bdev=sda3\0"
  621. #define CONFIG_LINUX \
  622. "setenv bootargs root=/dev/ram rw " \
  623. "console=$consoledev,$baudrate $othbootargs;" \
  624. "setenv ramdiskaddr 0x02000000;" \
  625. "setenv fdtaddr 0x00c00000;" \
  626. "setenv loadaddr 0x1000000;" \
  627. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  628. #define CONFIG_NFSBOOTCOMMAND \
  629. "setenv bootargs root=/dev/nfs rw " \
  630. "nfsroot=$serverip:$rootpath " \
  631. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  632. "console=$consoledev,$baudrate $othbootargs;" \
  633. "tftp $loadaddr $bootfile;" \
  634. "tftp $fdtaddr $fdtfile;" \
  635. "bootm $loadaddr - $fdtaddr"
  636. #define CONFIG_BOOTCOMMAND CONFIG_LINUX
  637. #include <asm/fsl_secure_boot.h>
  638. #endif /* __T1024RDB_H */