P1022DS.h 18 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2010-2012 Freescale Semiconductor, Inc.
  4. * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
  5. * Timur Tabi <timur@freescale.com>
  6. */
  7. #ifndef __CONFIG_H
  8. #define __CONFIG_H
  9. #include "../board/freescale/common/ics307_clk.h"
  10. #ifdef CONFIG_SDCARD
  11. #define CONFIG_SPL_FLUSH_IMAGE
  12. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  13. #define CONFIG_SPL_PAD_TO 0x20000
  14. #define CONFIG_SPL_MAX_SIZE (128 * 1024)
  15. #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
  16. #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
  17. #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
  18. #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
  19. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  20. #ifdef CONFIG_SPL_BUILD
  21. #define CONFIG_SPL_COMMON_INIT_DDR
  22. #endif
  23. #endif
  24. #ifdef CONFIG_SPIFLASH
  25. #define CONFIG_SPL_SPI_FLASH_MINIMAL
  26. #define CONFIG_SPL_FLUSH_IMAGE
  27. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  28. #define CONFIG_SPL_PAD_TO 0x20000
  29. #define CONFIG_SPL_MAX_SIZE (128 * 1024)
  30. #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
  31. #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
  32. #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
  33. #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
  34. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  35. #ifdef CONFIG_SPL_BUILD
  36. #define CONFIG_SPL_COMMON_INIT_DDR
  37. #endif
  38. #endif
  39. #define CONFIG_NAND_FSL_ELBC
  40. #define CONFIG_SYS_NAND_MAX_ECCPOS 56
  41. #define CONFIG_SYS_NAND_MAX_OOBFREE 5
  42. #ifdef CONFIG_MTD_RAW_NAND
  43. #ifdef CONFIG_TPL_BUILD
  44. #define CONFIG_SPL_FLUSH_IMAGE
  45. #define CONFIG_SPL_NAND_INIT
  46. #define CONFIG_SPL_COMMON_INIT_DDR
  47. #define CONFIG_SPL_MAX_SIZE (128 << 10)
  48. #define CONFIG_TPL_TEXT_BASE 0xf8f81000
  49. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  50. #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
  51. #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
  52. #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
  53. #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
  54. #elif defined(CONFIG_SPL_BUILD)
  55. #define CONFIG_SPL_INIT_MINIMAL
  56. #define CONFIG_SPL_FLUSH_IMAGE
  57. #define CONFIG_SPL_MAX_SIZE 4096
  58. #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
  59. #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
  60. #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
  61. #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
  62. #endif
  63. #define CONFIG_SPL_PAD_TO 0x20000
  64. #define CONFIG_TPL_PAD_TO 0x20000
  65. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  66. #endif
  67. /* High Level Configuration Options */
  68. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  69. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  70. #endif
  71. #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
  72. #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
  73. #define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */
  74. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  75. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  76. #define CONFIG_ENABLE_36BIT_PHYS
  77. #ifdef CONFIG_PHYS_64BIT
  78. #define CONFIG_ADDR_MAP
  79. #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
  80. #endif
  81. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
  82. #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
  83. #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
  84. /*
  85. * These can be toggled for performance analysis, otherwise use default.
  86. */
  87. #define CONFIG_L2_CACHE
  88. #define CONFIG_BTB
  89. #define CONFIG_SYS_MEMTEST_START 0x00000000
  90. #define CONFIG_SYS_MEMTEST_END 0x7fffffff
  91. #define CONFIG_SYS_CCSRBAR 0xffe00000
  92. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  93. /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
  94. SPL code*/
  95. #ifdef CONFIG_SPL_BUILD
  96. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  97. #endif
  98. /* DDR Setup */
  99. #define CONFIG_DDR_SPD
  100. #define CONFIG_VERY_BIG_RAM
  101. #ifdef CONFIG_DDR_ECC
  102. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  103. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  104. #endif
  105. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  106. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  107. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  108. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  109. /* I2C addresses of SPD EEPROMs */
  110. #define CONFIG_SYS_SPD_BUS_NUM 1
  111. #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
  112. /* These are used when DDR doesn't use SPD. */
  113. #define CONFIG_SYS_SDRAM_SIZE 2048
  114. #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
  115. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
  116. #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
  117. #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F
  118. #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202
  119. #define CONFIG_SYS_DDR_TIMING_3 0x00010000
  120. #define CONFIG_SYS_DDR_TIMING_0 0x40110104
  121. #define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746
  122. #define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca
  123. #define CONFIG_SYS_DDR_MODE_1 0x00441221
  124. #define CONFIG_SYS_DDR_MODE_2 0x00000000
  125. #define CONFIG_SYS_DDR_INTERVAL 0x0a280100
  126. #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
  127. #define CONFIG_SYS_DDR_CLK_CTRL 0x02800000
  128. #define CONFIG_SYS_DDR_CONTROL 0xc7000008
  129. #define CONFIG_SYS_DDR_CONTROL_2 0x24401041
  130. #define CONFIG_SYS_DDR_TIMING_4 0x00220001
  131. #define CONFIG_SYS_DDR_TIMING_5 0x02401400
  132. #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
  133. #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608
  134. /*
  135. * Memory map
  136. *
  137. * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
  138. * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable
  139. * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
  140. *
  141. * Localbus cacheable (TBD)
  142. * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
  143. *
  144. * Localbus non-cacheable
  145. * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
  146. * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
  147. * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable
  148. * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
  149. * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
  150. * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
  151. */
  152. /*
  153. * Local Bus Definitions
  154. */
  155. #define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */
  156. #ifdef CONFIG_PHYS_64BIT
  157. #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull
  158. #else
  159. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  160. #endif
  161. #define CONFIG_FLASH_BR_PRELIM \
  162. (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
  163. #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7)
  164. #ifdef CONFIG_MTD_RAW_NAND
  165. #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
  166. #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
  167. #else
  168. #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
  169. #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
  170. #endif
  171. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
  172. #define CONFIG_SYS_FLASH_QUIET_TEST
  173. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  174. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  175. #define CONFIG_SYS_MAX_FLASH_SECT 1024
  176. #ifndef CONFIG_SYS_MONITOR_BASE
  177. #ifdef CONFIG_TPL_BUILD
  178. #define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
  179. #elif defined(CONFIG_SPL_BUILD)
  180. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  181. #else
  182. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  183. #endif
  184. #endif
  185. #define CONFIG_SYS_FLASH_EMPTY_INFO
  186. /* Nand Flash */
  187. #if defined(CONFIG_NAND_FSL_ELBC)
  188. #define CONFIG_SYS_NAND_BASE 0xff800000
  189. #ifdef CONFIG_PHYS_64BIT
  190. #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
  191. #else
  192. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  193. #endif
  194. #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
  195. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  196. #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
  197. #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
  198. /* NAND flash config */
  199. #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  200. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  201. | BR_PS_8 /* Port Size = 8 bit */ \
  202. | BR_MS_FCM /* MSEL = FCM */ \
  203. | BR_V) /* valid */
  204. #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \
  205. | OR_FCM_PGS /* Large Page*/ \
  206. | OR_FCM_CSCT \
  207. | OR_FCM_CST \
  208. | OR_FCM_CHT \
  209. | OR_FCM_SCY_1 \
  210. | OR_FCM_TRLX \
  211. | OR_FCM_EHTR)
  212. #ifdef CONFIG_MTD_RAW_NAND
  213. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
  214. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  215. #else
  216. #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
  217. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  218. #endif
  219. #endif /* CONFIG_NAND_FSL_ELBC */
  220. #define CONFIG_HWCONFIG
  221. #define CONFIG_FSL_NGPIXIS
  222. #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
  223. #ifdef CONFIG_PHYS_64BIT
  224. #define PIXIS_BASE_PHYS 0xfffdf0000ull
  225. #else
  226. #define PIXIS_BASE_PHYS PIXIS_BASE
  227. #endif
  228. #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
  229. #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7)
  230. #define PIXIS_LBMAP_SWITCH 7
  231. #define PIXIS_LBMAP_MASK 0xF0
  232. #define PIXIS_LBMAP_ALTBANK 0x20
  233. #define PIXIS_SPD 0x07
  234. #define PIXIS_SPD_SYSCLK_MASK 0x07
  235. #define PIXIS_ELBC_SPI_MASK 0xc0
  236. #define PIXIS_SPI 0x80
  237. #define CONFIG_SYS_INIT_RAM_LOCK
  238. #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
  239. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
  240. #define CONFIG_SYS_GBL_DATA_OFFSET \
  241. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  242. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  243. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  244. #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
  245. /*
  246. * Config the L2 Cache as L2 SRAM
  247. */
  248. #if defined(CONFIG_SPL_BUILD)
  249. #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
  250. #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
  251. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  252. #define CONFIG_SYS_L2_SIZE (256 << 10)
  253. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  254. #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
  255. #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
  256. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
  257. #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
  258. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
  259. #elif defined(CONFIG_MTD_RAW_NAND)
  260. #ifdef CONFIG_TPL_BUILD
  261. #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
  262. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  263. #define CONFIG_SYS_L2_SIZE (256 << 10)
  264. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  265. #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
  266. #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
  267. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
  268. #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
  269. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
  270. #else
  271. #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
  272. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  273. #define CONFIG_SYS_L2_SIZE (256 << 10)
  274. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  275. #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
  276. #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
  277. #endif
  278. #endif
  279. #endif
  280. /*
  281. * Serial Port
  282. */
  283. #define CONFIG_SYS_NS16550_SERIAL
  284. #define CONFIG_SYS_NS16550_REG_SIZE 1
  285. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  286. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
  287. #define CONFIG_NS16550_MIN_FUNCTIONS
  288. #endif
  289. #define CONFIG_SYS_BAUDRATE_TABLE \
  290. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  291. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  292. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  293. /* Video */
  294. #ifdef CONFIG_FSL_DIU_FB
  295. #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
  296. #define CONFIG_VIDEO_LOGO
  297. #define CONFIG_VIDEO_BMP_LOGO
  298. #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
  299. /*
  300. * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
  301. * disable empty flash sector detection, which is I/O-intensive.
  302. */
  303. #undef CONFIG_SYS_FLASH_EMPTY_INFO
  304. #endif
  305. #ifdef CONFIG_ATI
  306. #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
  307. #define CONFIG_BIOSEMU
  308. #define CONFIG_ATI_RADEON_FB
  309. #define CONFIG_VIDEO_LOGO
  310. #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
  311. #endif
  312. /* I2C */
  313. #define CONFIG_SYS_I2C
  314. #define CONFIG_SYS_I2C_FSL
  315. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  316. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  317. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  318. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  319. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  320. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  321. #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}}
  322. /*
  323. * I2C2 EEPROM
  324. */
  325. #define CONFIG_ID_EEPROM
  326. #define CONFIG_SYS_I2C_EEPROM_NXID
  327. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  328. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  329. #define CONFIG_SYS_EEPROM_BUS_NUM 1
  330. /*
  331. * General PCI
  332. * Memory space is mapped 1-1, but I/O space must start from 0.
  333. */
  334. /* controller 1, Slot 2, tgtid 1, Base address a000 */
  335. #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
  336. #ifdef CONFIG_PHYS_64BIT
  337. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  338. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
  339. #else
  340. #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
  341. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
  342. #endif
  343. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  344. #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
  345. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  346. #ifdef CONFIG_PHYS_64BIT
  347. #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
  348. #else
  349. #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
  350. #endif
  351. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  352. /* controller 2, direct to uli, tgtid 2, Base address 9000 */
  353. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  354. #ifdef CONFIG_PHYS_64BIT
  355. #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
  356. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  357. #else
  358. #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
  359. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
  360. #endif
  361. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
  362. #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
  363. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  364. #ifdef CONFIG_PHYS_64BIT
  365. #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
  366. #else
  367. #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
  368. #endif
  369. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  370. /* controller 3, Slot 1, tgtid 3, Base address b000 */
  371. #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
  372. #ifdef CONFIG_PHYS_64BIT
  373. #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  374. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
  375. #else
  376. #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
  377. #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
  378. #endif
  379. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
  380. #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
  381. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  382. #ifdef CONFIG_PHYS_64BIT
  383. #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
  384. #else
  385. #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
  386. #endif
  387. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  388. #ifdef CONFIG_PCI
  389. #define CONFIG_PCI_INDIRECT_BRIDGE
  390. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  391. #endif
  392. /* SATA */
  393. #define CONFIG_FSL_SATA_V2
  394. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  395. #define CONFIG_SATA1
  396. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  397. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  398. #define CONFIG_SATA2
  399. #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  400. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  401. #ifdef CONFIG_FSL_SATA
  402. #define CONFIG_LBA48
  403. #endif
  404. #ifdef CONFIG_MMC
  405. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  406. #endif
  407. #ifdef CONFIG_TSEC_ENET
  408. #define CONFIG_TSECV2
  409. #define CONFIG_TSEC1 1
  410. #define CONFIG_TSEC1_NAME "eTSEC1"
  411. #define CONFIG_TSEC2 1
  412. #define CONFIG_TSEC2_NAME "eTSEC2"
  413. #define TSEC1_PHY_ADDR 1
  414. #define TSEC2_PHY_ADDR 2
  415. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  416. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  417. #define TSEC1_PHYIDX 0
  418. #define TSEC2_PHYIDX 0
  419. #define CONFIG_ETHPRIME "eTSEC1"
  420. #endif
  421. /*
  422. * Dynamic MTD Partition support with mtdparts
  423. */
  424. /*
  425. * Environment
  426. */
  427. #if defined(CONFIG_SDCARD)
  428. #define CONFIG_FSL_FIXED_MMC_LOCATION
  429. #define CONFIG_SYS_MMC_ENV_DEV 0
  430. #elif defined(CONFIG_MTD_RAW_NAND)
  431. #ifdef CONFIG_TPL_BUILD
  432. #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
  433. #endif
  434. #elif defined(CONFIG_SYS_RAMBOOT)
  435. #define SPL_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
  436. #endif
  437. #define CONFIG_LOADS_ECHO
  438. #define CONFIG_SYS_LOADS_BAUD_CHANGE
  439. /*
  440. * USB
  441. */
  442. #define CONFIG_HAS_FSL_DR_USB
  443. #ifdef CONFIG_HAS_FSL_DR_USB
  444. #ifdef CONFIG_USB_EHCI_HCD
  445. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  446. #define CONFIG_USB_EHCI_FSL
  447. #endif
  448. #endif
  449. /*
  450. * Miscellaneous configurable options
  451. */
  452. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  453. /*
  454. * For booting Linux, the board info and command line data
  455. * have to be in the first 64 MB of memory, since this is
  456. * the maximum mapped by the Linux kernel during initialization.
  457. */
  458. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
  459. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  460. #ifdef CONFIG_CMD_KGDB
  461. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  462. #endif
  463. /*
  464. * Environment Configuration
  465. */
  466. #define CONFIG_HOSTNAME "p1022ds"
  467. #define CONFIG_ROOTPATH "/opt/nfsroot"
  468. #define CONFIG_BOOTFILE "uImage"
  469. #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
  470. #define CONFIG_LOADADDR 1000000
  471. #define CONFIG_EXTRA_ENV_SETTINGS \
  472. "netdev=eth0\0" \
  473. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  474. "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  475. "tftpflash=tftpboot $loadaddr $uboot && " \
  476. "protect off $ubootaddr +$filesize && " \
  477. "erase $ubootaddr +$filesize && " \
  478. "cp.b $loadaddr $ubootaddr $filesize && " \
  479. "protect on $ubootaddr +$filesize && " \
  480. "cmp.b $loadaddr $ubootaddr $filesize\0" \
  481. "consoledev=ttyS0\0" \
  482. "ramdiskaddr=2000000\0" \
  483. "ramdiskfile=rootfs.ext2.gz.uboot\0" \
  484. "fdtaddr=1e00000\0" \
  485. "fdtfile=p1022ds.dtb\0" \
  486. "bdev=sda3\0" \
  487. "hwconfig=esdhc;audclk:12\0"
  488. #define CONFIG_HDBOOT \
  489. "setenv bootargs root=/dev/$bdev rw " \
  490. "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
  491. "tftp $loadaddr $bootfile;" \
  492. "tftp $fdtaddr $fdtfile;" \
  493. "bootm $loadaddr - $fdtaddr"
  494. #define CONFIG_NFSBOOTCOMMAND \
  495. "setenv bootargs root=/dev/nfs rw " \
  496. "nfsroot=$serverip:$rootpath " \
  497. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  498. "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
  499. "tftp $loadaddr $bootfile;" \
  500. "tftp $fdtaddr $fdtfile;" \
  501. "bootm $loadaddr - $fdtaddr"
  502. #define CONFIG_RAMBOOTCOMMAND \
  503. "setenv bootargs root=/dev/ram rw " \
  504. "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
  505. "tftp $ramdiskaddr $ramdiskfile;" \
  506. "tftp $loadaddr $bootfile;" \
  507. "tftp $fdtaddr $fdtfile;" \
  508. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  509. #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
  510. #endif