P1010RDB.h 24 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2010-2011 Freescale Semiconductor, Inc.
  4. */
  5. /*
  6. * P010 RDB board configuration file
  7. */
  8. #ifndef __CONFIG_H
  9. #define __CONFIG_H
  10. #include <asm/config_mpc85xx.h>
  11. #define CONFIG_NAND_FSL_IFC
  12. #ifdef CONFIG_SDCARD
  13. #define CONFIG_SPL_FLUSH_IMAGE
  14. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  15. #define CONFIG_SPL_PAD_TO 0x18000
  16. #define CONFIG_SPL_MAX_SIZE (96 * 1024)
  17. #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10)
  18. #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
  19. #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
  20. #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
  21. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  22. #ifdef CONFIG_SPL_BUILD
  23. #define CONFIG_SPL_COMMON_INIT_DDR
  24. #endif
  25. #endif
  26. #ifdef CONFIG_SPIFLASH
  27. #ifdef CONFIG_NXP_ESBC
  28. #define CONFIG_RAMBOOT_SPIFLASH
  29. #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
  30. #else
  31. #define CONFIG_SPL_SPI_FLASH_MINIMAL
  32. #define CONFIG_SPL_FLUSH_IMAGE
  33. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  34. #define CONFIG_SPL_PAD_TO 0x18000
  35. #define CONFIG_SPL_MAX_SIZE (96 * 1024)
  36. #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
  37. #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
  38. #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
  39. #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
  40. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  41. #ifdef CONFIG_SPL_BUILD
  42. #define CONFIG_SPL_COMMON_INIT_DDR
  43. #endif
  44. #endif
  45. #endif
  46. #ifdef CONFIG_MTD_RAW_NAND
  47. #ifdef CONFIG_NXP_ESBC
  48. #define CONFIG_SPL_INIT_MINIMAL
  49. #define CONFIG_SPL_FLUSH_IMAGE
  50. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  51. #define CONFIG_SPL_MAX_SIZE 8192
  52. #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
  53. #define CONFIG_SPL_RELOC_STACK 0x00100000
  54. #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
  55. #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
  56. #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
  57. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0
  58. #else
  59. #ifdef CONFIG_TPL_BUILD
  60. #define CONFIG_SPL_FLUSH_IMAGE
  61. #define CONFIG_SPL_NAND_INIT
  62. #define CONFIG_SPL_COMMON_INIT_DDR
  63. #define CONFIG_SPL_MAX_SIZE (128 << 10)
  64. #define CONFIG_TPL_TEXT_BASE 0xD0001000
  65. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  66. #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
  67. #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
  68. #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
  69. #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
  70. #elif defined(CONFIG_SPL_BUILD)
  71. #define CONFIG_SPL_INIT_MINIMAL
  72. #define CONFIG_SPL_NAND_MINIMAL
  73. #define CONFIG_SPL_FLUSH_IMAGE
  74. #define CONFIG_SPL_MAX_SIZE 8192
  75. #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
  76. #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000
  77. #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000
  78. #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
  79. #endif
  80. #define CONFIG_SPL_PAD_TO 0x20000
  81. #define CONFIG_TPL_PAD_TO 0x20000
  82. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  83. #endif
  84. #endif
  85. #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */
  86. #define CONFIG_RAMBOOT_NAND
  87. #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
  88. #endif
  89. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  90. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  91. #endif
  92. #ifdef CONFIG_TPL_BUILD
  93. #define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
  94. #elif defined(CONFIG_SPL_BUILD)
  95. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  96. #else
  97. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  98. #endif
  99. /* High Level Configuration Options */
  100. #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
  101. #if defined(CONFIG_PCI)
  102. #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
  103. #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
  104. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  105. #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
  106. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  107. /*
  108. * PCI Windows
  109. * Memory space is mapped 1-1, but I/O space must start from 0.
  110. */
  111. /* controller 1, Slot 1, tgtid 1, Base address a000 */
  112. #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot"
  113. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  114. #ifdef CONFIG_PHYS_64BIT
  115. #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
  116. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  117. #else
  118. #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
  119. #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
  120. #endif
  121. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  122. #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
  123. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  124. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  125. #ifdef CONFIG_PHYS_64BIT
  126. #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
  127. #else
  128. #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
  129. #endif
  130. /* controller 2, Slot 2, tgtid 2, Base address 9000 */
  131. #if defined(CONFIG_TARGET_P1010RDB_PA)
  132. #define CONFIG_SYS_PCIE2_NAME "PCIe Slot"
  133. #elif defined(CONFIG_TARGET_P1010RDB_PB)
  134. #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot"
  135. #endif
  136. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  137. #ifdef CONFIG_PHYS_64BIT
  138. #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
  139. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  140. #else
  141. #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
  142. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
  143. #endif
  144. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
  145. #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
  146. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  147. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  148. #ifdef CONFIG_PHYS_64BIT
  149. #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
  150. #else
  151. #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
  152. #endif
  153. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  154. #endif
  155. #define CONFIG_ENV_OVERWRITE
  156. #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */
  157. #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */
  158. #define CONFIG_HWCONFIG
  159. /*
  160. * These can be toggled for performance analysis, otherwise use default.
  161. */
  162. #define CONFIG_L2_CACHE /* toggle L2 cache */
  163. #define CONFIG_BTB /* toggle branch predition */
  164. #define CONFIG_ENABLE_36BIT_PHYS
  165. #ifdef CONFIG_PHYS_64BIT
  166. #define CONFIG_ADDR_MAP 1
  167. #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
  168. #endif
  169. #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
  170. #define CONFIG_SYS_MEMTEST_END 0x1fffffff
  171. /* DDR Setup */
  172. #define CONFIG_SYS_DDR_RAW_TIMING
  173. #define CONFIG_DDR_SPD
  174. #define CONFIG_SYS_SPD_BUS_NUM 1
  175. #define SPD_EEPROM_ADDRESS 0x52
  176. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  177. #ifndef __ASSEMBLY__
  178. extern unsigned long get_sdram_size(void);
  179. #endif
  180. #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
  181. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  182. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  183. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  184. #define CONFIG_CHIP_SELECTS_PER_CTRL 1
  185. /* DDR3 Controller Settings */
  186. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
  187. #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
  188. #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
  189. #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
  190. #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
  191. #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
  192. #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
  193. #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
  194. #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
  195. #define CONFIG_SYS_DDR_RCW_1 0x00000000
  196. #define CONFIG_SYS_DDR_RCW_2 0x00000000
  197. #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */
  198. #define CONFIG_SYS_DDR_CONTROL_2 0x24401000
  199. #define CONFIG_SYS_DDR_TIMING_4 0x00000001
  200. #define CONFIG_SYS_DDR_TIMING_5 0x03402400
  201. #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
  202. #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
  203. #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
  204. #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF
  205. #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
  206. #define CONFIG_SYS_DDR_MODE_1_800 0x00441420
  207. #define CONFIG_SYS_DDR_MODE_2_800 0x00000000
  208. #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100
  209. #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
  210. /* settings for DDR3 at 667MT/s */
  211. #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000
  212. #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004
  213. #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544
  214. #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD
  215. #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000
  216. #define CONFIG_SYS_DDR_MODE_1_667 0x00441210
  217. #define CONFIG_SYS_DDR_MODE_2_667 0x00000000
  218. #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000
  219. #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608
  220. #define CONFIG_SYS_CCSRBAR 0xffe00000
  221. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  222. /* Don't relocate CCSRBAR while in NAND_SPL */
  223. #ifdef CONFIG_SPL_BUILD
  224. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  225. #endif
  226. /*
  227. * Memory map
  228. *
  229. * 0x0000_0000 0x3fff_ffff DDR 1G cacheable
  230. * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable
  231. * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
  232. *
  233. * Localbus non-cacheable
  234. * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable
  235. * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
  236. * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
  237. * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
  238. */
  239. /*
  240. * IFC Definitions
  241. */
  242. /* NOR Flash on IFC */
  243. #define CONFIG_SYS_FLASH_BASE 0xee000000
  244. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
  245. #ifdef CONFIG_PHYS_64BIT
  246. #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  247. #else
  248. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  249. #endif
  250. #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  251. CSPR_PORT_SIZE_16 | \
  252. CSPR_MSEL_NOR | \
  253. CSPR_V)
  254. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024)
  255. #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7)
  256. /* NOR Flash Timing Params */
  257. #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \
  258. FTIM0_NOR_TEADC(0x5) | \
  259. FTIM0_NOR_TEAHC(0x5)
  260. #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \
  261. FTIM1_NOR_TRAD_NOR(0x0f)
  262. #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \
  263. FTIM2_NOR_TCH(0x4) | \
  264. FTIM2_NOR_TWP(0x1c)
  265. #define CONFIG_SYS_NOR_FTIM3 0x0
  266. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
  267. #define CONFIG_SYS_FLASH_QUIET_TEST
  268. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  269. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  270. #undef CONFIG_SYS_FLASH_CHECKSUM
  271. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  272. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  273. /* CFI for NOR Flash */
  274. #define CONFIG_SYS_FLASH_EMPTY_INFO
  275. /* NAND Flash on IFC */
  276. #define CONFIG_SYS_NAND_BASE 0xff800000
  277. #ifdef CONFIG_PHYS_64BIT
  278. #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
  279. #else
  280. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  281. #endif
  282. #define CONFIG_MTD_PARTITION
  283. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  284. | CSPR_PORT_SIZE_8 \
  285. | CSPR_MSEL_NAND \
  286. | CSPR_V)
  287. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  288. #if defined(CONFIG_TARGET_P1010RDB_PA)
  289. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  290. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  291. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  292. | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \
  293. | CSOR_NAND_PGS_512 /* Page Size = 512b */ \
  294. | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \
  295. | CSOR_NAND_PB(32)) /* 32 Pages Per Block */
  296. #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
  297. #elif defined(CONFIG_TARGET_P1010RDB_PB)
  298. #define CONFIG_SYS_NAND_ONFI_DETECTION
  299. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  300. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  301. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  302. | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
  303. | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
  304. | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
  305. | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */
  306. #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
  307. #endif
  308. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  309. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  310. #if defined(CONFIG_TARGET_P1010RDB_PA)
  311. /* NAND Flash Timing Params */
  312. #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
  313. FTIM0_NAND_TWP(0x0C) | \
  314. FTIM0_NAND_TWCHT(0x04) | \
  315. FTIM0_NAND_TWH(0x05)
  316. #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
  317. FTIM1_NAND_TWBE(0x1d) | \
  318. FTIM1_NAND_TRR(0x07) | \
  319. FTIM1_NAND_TRP(0x0c)
  320. #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
  321. FTIM2_NAND_TREH(0x05) | \
  322. FTIM2_NAND_TWHRE(0x0f)
  323. #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
  324. #elif defined(CONFIG_TARGET_P1010RDB_PB)
  325. /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
  326. /* ONFI NAND Flash mode0 Timing Params */
  327. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
  328. FTIM0_NAND_TWP(0x18) | \
  329. FTIM0_NAND_TWCHT(0x07) | \
  330. FTIM0_NAND_TWH(0x0a))
  331. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \
  332. FTIM1_NAND_TWBE(0x39) | \
  333. FTIM1_NAND_TRR(0x0e) | \
  334. FTIM1_NAND_TRP(0x18))
  335. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  336. FTIM2_NAND_TREH(0x0a) | \
  337. FTIM2_NAND_TWHRE(0x1e))
  338. #define CONFIG_SYS_NAND_FTIM3 0x0
  339. #endif
  340. #define CONFIG_SYS_NAND_DDR_LAW 11
  341. /* Set up IFC registers for boot location NOR/NAND */
  342. #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
  343. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  344. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  345. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  346. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  347. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  348. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  349. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  350. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
  351. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  352. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  353. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  354. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  355. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  356. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  357. #else
  358. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
  359. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  360. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  361. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  362. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  363. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  364. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  365. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
  366. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
  367. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
  368. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
  369. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
  370. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
  371. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
  372. #endif
  373. /* CPLD on IFC */
  374. #define CONFIG_SYS_CPLD_BASE 0xffb00000
  375. #ifdef CONFIG_PHYS_64BIT
  376. #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull
  377. #else
  378. #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
  379. #endif
  380. #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
  381. | CSPR_PORT_SIZE_8 \
  382. | CSPR_MSEL_GPCM \
  383. | CSPR_V)
  384. #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
  385. #define CONFIG_SYS_CSOR3 0x0
  386. /* CPLD Timing parameters for IFC CS3 */
  387. #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  388. FTIM0_GPCM_TEADC(0x0e) | \
  389. FTIM0_GPCM_TEAHC(0x0e))
  390. #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
  391. FTIM1_GPCM_TRAD(0x1f))
  392. #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
  393. FTIM2_GPCM_TCH(0x8) | \
  394. FTIM2_GPCM_TWP(0x1f))
  395. #define CONFIG_SYS_CS3_FTIM3 0x0
  396. #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
  397. defined(CONFIG_RAMBOOT_NAND)
  398. #define CONFIG_SYS_RAMBOOT
  399. #else
  400. #undef CONFIG_SYS_RAMBOOT
  401. #endif
  402. #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
  403. #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)
  404. #define CONFIG_A003399_NOR_WORKAROUND
  405. #endif
  406. #endif
  407. #define CONFIG_SYS_INIT_RAM_LOCK
  408. #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
  409. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
  410. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
  411. - GENERATED_GBL_DATA_SIZE)
  412. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  413. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  414. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
  415. /*
  416. * Config the L2 Cache as L2 SRAM
  417. */
  418. #if defined(CONFIG_SPL_BUILD)
  419. #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
  420. #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
  421. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  422. #define CONFIG_SYS_L2_SIZE (256 << 10)
  423. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  424. #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
  425. #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
  426. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
  427. #define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10)
  428. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
  429. #elif defined(CONFIG_MTD_RAW_NAND)
  430. #ifdef CONFIG_TPL_BUILD
  431. #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
  432. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  433. #define CONFIG_SYS_L2_SIZE (256 << 10)
  434. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  435. #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
  436. #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
  437. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
  438. #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
  439. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
  440. #else
  441. #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
  442. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  443. #define CONFIG_SYS_L2_SIZE (256 << 10)
  444. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  445. #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
  446. #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
  447. #endif
  448. #endif
  449. #endif
  450. /* Serial Port */
  451. #undef CONFIG_SERIAL_SOFTWARE_FIFO
  452. #define CONFIG_SYS_NS16550_SERIAL
  453. #define CONFIG_SYS_NS16550_REG_SIZE 1
  454. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  455. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
  456. #define CONFIG_NS16550_MIN_FUNCTIONS
  457. #endif
  458. #define CONFIG_SYS_BAUDRATE_TABLE \
  459. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  460. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  461. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  462. /* I2C */
  463. #define CONFIG_SYS_I2C
  464. #define CONFIG_SYS_I2C_FSL
  465. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  466. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  467. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  468. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  469. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  470. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  471. #define I2C_PCA9557_ADDR1 0x18
  472. #define I2C_PCA9557_ADDR2 0x19
  473. #define I2C_PCA9557_BUS_NUM 0
  474. /* I2C EEPROM */
  475. #if defined(CONFIG_TARGET_P1010RDB_PB)
  476. #define CONFIG_ID_EEPROM
  477. #ifdef CONFIG_ID_EEPROM
  478. #define CONFIG_SYS_I2C_EEPROM_NXID
  479. #endif
  480. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  481. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  482. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  483. #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */
  484. #endif
  485. /* enable read and write access to EEPROM */
  486. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  487. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  488. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  489. /* RTC */
  490. #define CONFIG_RTC_PT7C4338
  491. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  492. /*
  493. * SPI interface will not be available in case of NAND boot SPI CS0 will be
  494. * used for SLIC
  495. */
  496. #if !defined(CONFIG_MTD_RAW_NAND) || !defined(CONFIG_NAND_SECBOOT)
  497. /* eSPI - Enhanced SPI */
  498. #endif
  499. #if defined(CONFIG_TSEC_ENET)
  500. #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
  501. #define CONFIG_TSEC1 1
  502. #define CONFIG_TSEC1_NAME "eTSEC1"
  503. #define CONFIG_TSEC2 1
  504. #define CONFIG_TSEC2_NAME "eTSEC2"
  505. #define CONFIG_TSEC3 1
  506. #define CONFIG_TSEC3_NAME "eTSEC3"
  507. #define TSEC1_PHY_ADDR 1
  508. #define TSEC2_PHY_ADDR 0
  509. #define TSEC3_PHY_ADDR 2
  510. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  511. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  512. #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  513. #define TSEC1_PHYIDX 0
  514. #define TSEC2_PHYIDX 0
  515. #define TSEC3_PHYIDX 0
  516. #define CONFIG_ETHPRIME "eTSEC1"
  517. /* TBI PHY configuration for SGMII mode */
  518. #define CONFIG_TSEC_TBICR_SETTINGS ( \
  519. TBICR_PHY_RESET \
  520. | TBICR_ANEG_ENABLE \
  521. | TBICR_FULL_DUPLEX \
  522. | TBICR_SPEED1_SET \
  523. )
  524. #endif /* CONFIG_TSEC_ENET */
  525. /* SATA */
  526. #define CONFIG_FSL_SATA_V2
  527. #ifdef CONFIG_FSL_SATA
  528. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  529. #define CONFIG_SATA1
  530. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  531. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  532. #define CONFIG_SATA2
  533. #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  534. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  535. #define CONFIG_LBA48
  536. #endif /* #ifdef CONFIG_FSL_SATA */
  537. #ifdef CONFIG_MMC
  538. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  539. #endif
  540. #define CONFIG_HAS_FSL_DR_USB
  541. #if defined(CONFIG_HAS_FSL_DR_USB)
  542. #ifdef CONFIG_USB_EHCI_HCD
  543. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  544. #define CONFIG_USB_EHCI_FSL
  545. #endif
  546. #endif
  547. /*
  548. * Environment
  549. */
  550. #if defined(CONFIG_SDCARD)
  551. #define CONFIG_FSL_FIXED_MMC_LOCATION
  552. #define CONFIG_SYS_MMC_ENV_DEV 0
  553. #elif defined(CONFIG_MTD_RAW_NAND)
  554. #ifdef CONFIG_TPL_BUILD
  555. #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
  556. #else
  557. #if defined(CONFIG_TARGET_P1010RDB_PA)
  558. #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
  559. #elif defined(CONFIG_TARGET_P1010RDB_PB)
  560. #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */
  561. #endif
  562. #endif
  563. #endif
  564. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  565. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  566. #undef CONFIG_WATCHDOG /* watchdog disabled */
  567. #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \
  568. || defined(CONFIG_FSL_SATA)
  569. #endif
  570. /*
  571. * Miscellaneous configurable options
  572. */
  573. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  574. /*
  575. * For booting Linux, the board info and command line data
  576. * have to be in the first 64 MB of memory, since this is
  577. * the maximum mapped by the Linux kernel during initialization.
  578. */
  579. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
  580. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  581. #if defined(CONFIG_CMD_KGDB)
  582. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  583. #endif
  584. /*
  585. * Environment Configuration
  586. */
  587. #if defined(CONFIG_TSEC_ENET)
  588. #define CONFIG_HAS_ETH0
  589. #define CONFIG_HAS_ETH1
  590. #define CONFIG_HAS_ETH2
  591. #endif
  592. #define CONFIG_ROOTPATH "/opt/nfsroot"
  593. #define CONFIG_BOOTFILE "uImage"
  594. #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
  595. /* default location for tftp and bootm */
  596. #define CONFIG_LOADADDR 1000000
  597. #define CONFIG_EXTRA_ENV_SETTINGS \
  598. "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
  599. "netdev=eth0\0" \
  600. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  601. "loadaddr=1000000\0" \
  602. "consoledev=ttyS0\0" \
  603. "ramdiskaddr=2000000\0" \
  604. "ramdiskfile=rootfs.ext2.gz.uboot\0" \
  605. "fdtaddr=1e00000\0" \
  606. "fdtfile=p1010rdb.dtb\0" \
  607. "bdev=sda1\0" \
  608. "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \
  609. "othbootargs=ramdisk_size=600000\0" \
  610. "usbfatboot=setenv bootargs root=/dev/ram rw " \
  611. "console=$consoledev,$baudrate $othbootargs; " \
  612. "usb start;" \
  613. "fatload usb 0:2 $loadaddr $bootfile;" \
  614. "fatload usb 0:2 $fdtaddr $fdtfile;" \
  615. "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
  616. "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
  617. "usbext2boot=setenv bootargs root=/dev/ram rw " \
  618. "console=$consoledev,$baudrate $othbootargs; " \
  619. "usb start;" \
  620. "ext2load usb 0:4 $loadaddr $bootfile;" \
  621. "ext2load usb 0:4 $fdtaddr $fdtfile;" \
  622. "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
  623. "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
  624. CONFIG_BOOTMODE
  625. #if defined(CONFIG_TARGET_P1010RDB_PA)
  626. #define CONFIG_BOOTMODE \
  627. "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
  628. "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
  629. "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
  630. "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
  631. "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
  632. "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
  633. #elif defined(CONFIG_TARGET_P1010RDB_PB)
  634. #define CONFIG_BOOTMODE \
  635. "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
  636. "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
  637. "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
  638. "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
  639. "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
  640. "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
  641. "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
  642. "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
  643. "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
  644. "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
  645. #endif
  646. #define CONFIG_RAMBOOTCOMMAND \
  647. "setenv bootargs root=/dev/ram rw " \
  648. "console=$consoledev,$baudrate $othbootargs; " \
  649. "tftp $ramdiskaddr $ramdiskfile;" \
  650. "tftp $loadaddr $bootfile;" \
  651. "tftp $fdtaddr $fdtfile;" \
  652. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  653. #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
  654. #include <asm/fsl_secure_boot.h>
  655. #endif /* __CONFIG_H */