MPC8572DS.h 20 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc.
  4. */
  5. /*
  6. * mpc8572ds board configuration file
  7. *
  8. */
  9. #ifndef __CONFIG_H
  10. #define __CONFIG_H
  11. #include "../board/freescale/common/ics307_clk.h"
  12. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  13. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  14. #endif
  15. #ifndef CONFIG_SYS_MONITOR_BASE
  16. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  17. #endif
  18. /* High Level Configuration Options */
  19. #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
  20. #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
  21. #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
  22. #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
  23. #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
  24. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  25. #define CONFIG_ENV_OVERWRITE
  26. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
  27. #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */
  28. #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
  29. /*
  30. * These can be toggled for performance analysis, otherwise use default.
  31. */
  32. #define CONFIG_L2_CACHE /* toggle L2 cache */
  33. #define CONFIG_BTB /* toggle branch predition */
  34. #define CONFIG_ENABLE_36BIT_PHYS 1
  35. #ifdef CONFIG_PHYS_64BIT
  36. #define CONFIG_ADDR_MAP 1
  37. #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
  38. #endif
  39. #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
  40. #define CONFIG_SYS_MEMTEST_END 0x7fffffff
  41. /*
  42. * Config the L2 Cache as L2 SRAM
  43. */
  44. #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
  45. #ifdef CONFIG_PHYS_64BIT
  46. #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
  47. #else
  48. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  49. #endif
  50. #define CONFIG_SYS_L2_SIZE (512 << 10)
  51. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  52. #define CONFIG_SYS_CCSRBAR 0xffe00000
  53. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  54. #if defined(CONFIG_NAND_SPL)
  55. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  56. #endif
  57. /* DDR Setup */
  58. #define CONFIG_VERY_BIG_RAM
  59. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
  60. #define CONFIG_DDR_SPD
  61. #define CONFIG_DDR_ECC
  62. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  63. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  64. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  65. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  66. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  67. #define CONFIG_CHIP_SELECTS_PER_CTRL 2
  68. /* I2C addresses of SPD EEPROMs */
  69. #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */
  70. #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
  71. #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */
  72. /* These are used when DDR doesn't use SPD. */
  73. #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
  74. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
  75. #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */
  76. #define CONFIG_SYS_DDR_TIMING_3 0x00020000
  77. #define CONFIG_SYS_DDR_TIMING_0 0x00260802
  78. #define CONFIG_SYS_DDR_TIMING_1 0x626b2634
  79. #define CONFIG_SYS_DDR_TIMING_2 0x062874cf
  80. #define CONFIG_SYS_DDR_MODE_1 0x00440462
  81. #define CONFIG_SYS_DDR_MODE_2 0x00000000
  82. #define CONFIG_SYS_DDR_INTERVAL 0x0c300100
  83. #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
  84. #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000
  85. #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
  86. #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
  87. #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */
  88. #define CONFIG_SYS_DDR_CONTROL2 0x24400000
  89. #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
  90. #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
  91. #define CONFIG_SYS_DDR_SBE 0x00010000
  92. /*
  93. * Make sure required options are set
  94. */
  95. #ifndef CONFIG_SPD_EEPROM
  96. #error ("CONFIG_SPD_EEPROM is required")
  97. #endif
  98. #undef CONFIG_CLOCKS_IN_MHZ
  99. /*
  100. * Memory map
  101. *
  102. * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
  103. * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
  104. * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
  105. * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
  106. *
  107. * Localbus cacheable (TBD)
  108. * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
  109. *
  110. * Localbus non-cacheable
  111. * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
  112. * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
  113. * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
  114. * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
  115. * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
  116. * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
  117. */
  118. /*
  119. * Local Bus Definitions
  120. */
  121. #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
  122. #ifdef CONFIG_PHYS_64BIT
  123. #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
  124. #else
  125. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  126. #endif
  127. #define CONFIG_FLASH_BR_PRELIM \
  128. (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
  129. #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
  130. #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
  131. #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
  132. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
  133. #define CONFIG_SYS_FLASH_QUIET_TEST
  134. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  135. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  136. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  137. #undef CONFIG_SYS_FLASH_CHECKSUM
  138. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  139. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  140. #undef CONFIG_SYS_RAMBOOT
  141. #define CONFIG_SYS_FLASH_EMPTY_INFO
  142. #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
  143. #define CONFIG_HWCONFIG /* enable hwconfig */
  144. #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
  145. #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
  146. #ifdef CONFIG_PHYS_64BIT
  147. #define PIXIS_BASE_PHYS 0xfffdf0000ull
  148. #else
  149. #define PIXIS_BASE_PHYS PIXIS_BASE
  150. #endif
  151. #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
  152. #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
  153. #define PIXIS_ID 0x0 /* Board ID at offset 0 */
  154. #define PIXIS_VER 0x1 /* Board version at offset 1 */
  155. #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
  156. #define PIXIS_CSR 0x3 /* PIXIS General control/status register */
  157. #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
  158. #define PIXIS_PWR 0x5 /* PIXIS Power status register */
  159. #define PIXIS_AUX 0x6 /* Auxiliary 1 register */
  160. #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
  161. #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
  162. #define PIXIS_VCTL 0x10 /* VELA Control Register */
  163. #define PIXIS_VSTAT 0x11 /* VELA Status Register */
  164. #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
  165. #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
  166. #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
  167. #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
  168. #define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */
  169. #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
  170. #define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */
  171. #define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */
  172. #define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */
  173. #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
  174. #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
  175. #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
  176. #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */
  177. #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */
  178. #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */
  179. #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */
  180. #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */
  181. #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */
  182. #define PIXIS_VWATCH 0x24 /* Watchdog Register */
  183. #define PIXIS_LED 0x25 /* LED Register */
  184. #define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */
  185. /* old pixis referenced names */
  186. #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
  187. #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
  188. #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0
  189. #define PIXIS_VSPEED2_TSEC1SER 0x8
  190. #define PIXIS_VSPEED2_TSEC2SER 0x4
  191. #define PIXIS_VSPEED2_TSEC3SER 0x2
  192. #define PIXIS_VSPEED2_TSEC4SER 0x1
  193. #define PIXIS_VCFGEN1_TSEC1SER 0x20
  194. #define PIXIS_VCFGEN1_TSEC2SER 0x20
  195. #define PIXIS_VCFGEN1_TSEC3SER 0x20
  196. #define PIXIS_VCFGEN1_TSEC4SER 0x20
  197. #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \
  198. | PIXIS_VSPEED2_TSEC2SER \
  199. | PIXIS_VSPEED2_TSEC3SER \
  200. | PIXIS_VSPEED2_TSEC4SER)
  201. #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \
  202. | PIXIS_VCFGEN1_TSEC2SER \
  203. | PIXIS_VCFGEN1_TSEC3SER \
  204. | PIXIS_VCFGEN1_TSEC4SER)
  205. #define CONFIG_SYS_INIT_RAM_LOCK 1
  206. #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
  207. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
  208. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  209. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  210. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
  211. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
  212. #ifndef CONFIG_NAND_SPL
  213. #define CONFIG_SYS_NAND_BASE 0xffa00000
  214. #ifdef CONFIG_PHYS_64BIT
  215. #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
  216. #else
  217. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  218. #endif
  219. #else
  220. #define CONFIG_SYS_NAND_BASE 0xfff00000
  221. #ifdef CONFIG_PHYS_64BIT
  222. #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
  223. #else
  224. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  225. #endif
  226. #endif
  227. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
  228. CONFIG_SYS_NAND_BASE + 0x40000, \
  229. CONFIG_SYS_NAND_BASE + 0x80000,\
  230. CONFIG_SYS_NAND_BASE + 0xC0000}
  231. #define CONFIG_SYS_MAX_NAND_DEVICE 4
  232. #define CONFIG_NAND_FSL_ELBC 1
  233. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  234. #define CONFIG_SYS_NAND_MAX_OOBFREE 5
  235. #define CONFIG_SYS_NAND_MAX_ECCPOS 56
  236. /* NAND boot: 4K NAND loader config */
  237. #define CONFIG_SYS_NAND_SPL_SIZE 0x1000
  238. #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
  239. #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
  240. #define CONFIG_SYS_NAND_U_BOOT_START \
  241. (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
  242. #define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
  243. #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
  244. #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
  245. /* NAND flash config */
  246. #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  247. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  248. | BR_PS_8 /* Port Size = 8 bit */ \
  249. | BR_MS_FCM /* MSEL = FCM */ \
  250. | BR_V) /* valid */
  251. #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
  252. | OR_FCM_PGS /* Large Page*/ \
  253. | OR_FCM_CSCT \
  254. | OR_FCM_CST \
  255. | OR_FCM_CHT \
  256. | OR_FCM_SCY_1 \
  257. | OR_FCM_TRLX \
  258. | OR_FCM_EHTR)
  259. #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
  260. #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
  261. #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
  262. #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  263. #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
  264. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  265. | BR_PS_8 /* Port Size = 8 bit */ \
  266. | BR_MS_FCM /* MSEL = FCM */ \
  267. | BR_V) /* valid */
  268. #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  269. #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\
  270. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  271. | BR_PS_8 /* Port Size = 8 bit */ \
  272. | BR_MS_FCM /* MSEL = FCM */ \
  273. | BR_V) /* valid */
  274. #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  275. #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\
  276. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  277. | BR_PS_8 /* Port Size = 8 bit */ \
  278. | BR_MS_FCM /* MSEL = FCM */ \
  279. | BR_V) /* valid */
  280. #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  281. /* Serial Port - controlled on board with jumper J8
  282. * open - index 2
  283. * shorted - index 1
  284. */
  285. #define CONFIG_SYS_NS16550_SERIAL
  286. #define CONFIG_SYS_NS16550_REG_SIZE 1
  287. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  288. #ifdef CONFIG_NAND_SPL
  289. #define CONFIG_NS16550_MIN_FUNCTIONS
  290. #endif
  291. #define CONFIG_SYS_BAUDRATE_TABLE \
  292. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  293. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  294. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  295. /* I2C */
  296. #define CONFIG_SYS_I2C
  297. #define CONFIG_SYS_I2C_FSL
  298. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  299. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  300. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  301. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  302. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  303. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  304. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
  305. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  306. /*
  307. * I2C2 EEPROM
  308. */
  309. #define CONFIG_ID_EEPROM
  310. #ifdef CONFIG_ID_EEPROM
  311. #define CONFIG_SYS_I2C_EEPROM_NXID
  312. #endif
  313. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  314. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  315. #define CONFIG_SYS_EEPROM_BUS_NUM 1
  316. /*
  317. * General PCI
  318. * Memory space is mapped 1-1, but I/O space must start from 0.
  319. */
  320. /* controller 3, direct to uli, tgtid 3, Base address 8000 */
  321. #define CONFIG_SYS_PCIE3_NAME "ULI"
  322. #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
  323. #ifdef CONFIG_PHYS_64BIT
  324. #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  325. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
  326. #else
  327. #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
  328. #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
  329. #endif
  330. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
  331. #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
  332. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  333. #ifdef CONFIG_PHYS_64BIT
  334. #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
  335. #else
  336. #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
  337. #endif
  338. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  339. /* controller 2, Slot 2, tgtid 2, Base address 9000 */
  340. #define CONFIG_SYS_PCIE2_NAME "Slot 1"
  341. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  342. #ifdef CONFIG_PHYS_64BIT
  343. #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
  344. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  345. #else
  346. #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
  347. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
  348. #endif
  349. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
  350. #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
  351. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  352. #ifdef CONFIG_PHYS_64BIT
  353. #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
  354. #else
  355. #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
  356. #endif
  357. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  358. /* controller 1, Slot 1, tgtid 1, Base address a000 */
  359. #define CONFIG_SYS_PCIE1_NAME "Slot 2"
  360. #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
  361. #ifdef CONFIG_PHYS_64BIT
  362. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  363. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
  364. #else
  365. #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
  366. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
  367. #endif
  368. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  369. #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
  370. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  371. #ifdef CONFIG_PHYS_64BIT
  372. #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
  373. #else
  374. #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
  375. #endif
  376. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  377. #if defined(CONFIG_PCI)
  378. /*PCIE video card used*/
  379. #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
  380. /* video */
  381. #if defined(CONFIG_VIDEO)
  382. #define CONFIG_BIOSEMU
  383. #define CONFIG_ATI_RADEON_FB
  384. #define CONFIG_VIDEO_LOGO
  385. #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
  386. #endif
  387. #undef CONFIG_EEPRO100
  388. #undef CONFIG_TULIP
  389. #ifndef CONFIG_PCI_PNP
  390. #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
  391. #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS
  392. #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
  393. #endif
  394. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  395. #ifdef CONFIG_SCSI_AHCI
  396. #define CONFIG_SATA_ULI5288
  397. #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
  398. #define CONFIG_SYS_SCSI_MAX_LUN 1
  399. #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
  400. #endif /* SCSI */
  401. #endif /* CONFIG_PCI */
  402. #if defined(CONFIG_TSEC_ENET)
  403. #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
  404. #define CONFIG_TSEC1 1
  405. #define CONFIG_TSEC1_NAME "eTSEC1"
  406. #define CONFIG_TSEC2 1
  407. #define CONFIG_TSEC2_NAME "eTSEC2"
  408. #define CONFIG_TSEC3 1
  409. #define CONFIG_TSEC3_NAME "eTSEC3"
  410. #define CONFIG_TSEC4 1
  411. #define CONFIG_TSEC4_NAME "eTSEC4"
  412. #define CONFIG_PIXIS_SGMII_CMD
  413. #define CONFIG_FSL_SGMII_RISER 1
  414. #define SGMII_RISER_PHY_OFFSET 0x1c
  415. #ifdef CONFIG_FSL_SGMII_RISER
  416. #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */
  417. #endif
  418. #define TSEC1_PHY_ADDR 0
  419. #define TSEC2_PHY_ADDR 1
  420. #define TSEC3_PHY_ADDR 2
  421. #define TSEC4_PHY_ADDR 3
  422. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  423. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  424. #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  425. #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  426. #define TSEC1_PHYIDX 0
  427. #define TSEC2_PHYIDX 0
  428. #define TSEC3_PHYIDX 0
  429. #define TSEC4_PHYIDX 0
  430. #define CONFIG_ETHPRIME "eTSEC1"
  431. #endif /* CONFIG_TSEC_ENET */
  432. /*
  433. * Environment
  434. */
  435. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  436. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  437. /*
  438. * USB
  439. */
  440. #ifdef CONFIG_USB_EHCI_HCD
  441. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  442. #define CONFIG_PCI_EHCI_DEVICE 0
  443. #endif
  444. #undef CONFIG_WATCHDOG /* watchdog disabled */
  445. /*
  446. * Miscellaneous configurable options
  447. */
  448. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  449. /*
  450. * For booting Linux, the board info and command line data
  451. * have to be in the first 64 MB of memory, since this is
  452. * the maximum mapped by the Linux kernel during initialization.
  453. */
  454. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
  455. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  456. #if defined(CONFIG_CMD_KGDB)
  457. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  458. #endif
  459. /*
  460. * Environment Configuration
  461. */
  462. #if defined(CONFIG_TSEC_ENET)
  463. #define CONFIG_HAS_ETH0
  464. #define CONFIG_HAS_ETH1
  465. #define CONFIG_HAS_ETH2
  466. #define CONFIG_HAS_ETH3
  467. #endif
  468. #define CONFIG_IPADDR 192.168.1.254
  469. #define CONFIG_HOSTNAME "unknown"
  470. #define CONFIG_ROOTPATH "/opt/nfsroot"
  471. #define CONFIG_BOOTFILE "uImage"
  472. #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
  473. #define CONFIG_SERVERIP 192.168.1.1
  474. #define CONFIG_GATEWAYIP 192.168.1.1
  475. #define CONFIG_NETMASK 255.255.255.0
  476. /* default location for tftp and bootm */
  477. #define CONFIG_LOADADDR 1000000
  478. #define CONFIG_EXTRA_ENV_SETTINGS \
  479. "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \
  480. "netdev=eth0\0" \
  481. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  482. "tftpflash=tftpboot $loadaddr $uboot; " \
  483. "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
  484. " +$filesize; " \
  485. "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
  486. " +$filesize; " \
  487. "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  488. " $filesize; " \
  489. "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
  490. " +$filesize; " \
  491. "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  492. " $filesize\0" \
  493. "consoledev=ttyS0\0" \
  494. "ramdiskaddr=2000000\0" \
  495. "ramdiskfile=8572ds/ramdisk.uboot\0" \
  496. "fdtaddr=1e00000\0" \
  497. "fdtfile=8572ds/mpc8572ds.dtb\0" \
  498. "bdev=sda3\0"
  499. #define CONFIG_HDBOOT \
  500. "setenv bootargs root=/dev/$bdev rw " \
  501. "console=$consoledev,$baudrate $othbootargs;" \
  502. "tftp $loadaddr $bootfile;" \
  503. "tftp $fdtaddr $fdtfile;" \
  504. "bootm $loadaddr - $fdtaddr"
  505. #define CONFIG_NFSBOOTCOMMAND \
  506. "setenv bootargs root=/dev/nfs rw " \
  507. "nfsroot=$serverip:$rootpath " \
  508. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  509. "console=$consoledev,$baudrate $othbootargs;" \
  510. "tftp $loadaddr $bootfile;" \
  511. "tftp $fdtaddr $fdtfile;" \
  512. "bootm $loadaddr - $fdtaddr"
  513. #define CONFIG_RAMBOOTCOMMAND \
  514. "setenv bootargs root=/dev/ram rw " \
  515. "console=$consoledev,$baudrate $othbootargs;" \
  516. "tftp $ramdiskaddr $ramdiskfile;" \
  517. "tftp $loadaddr $bootfile;" \
  518. "tftp $fdtaddr $fdtfile;" \
  519. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  520. #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
  521. #endif /* __CONFIG_H */