MPC8569MDS.h 17 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2009-2011 Freescale Semiconductor, Inc.
  4. */
  5. /*
  6. * mpc8569mds board configuration file
  7. */
  8. #ifndef __CONFIG_H
  9. #define __CONFIG_H
  10. #define CONFIG_SYS_SRIO
  11. #define CONFIG_SRIO1 /* SRIO port 1 */
  12. #define CONFIG_PCIE1 1 /* PCIE controller */
  13. #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
  14. #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
  15. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  16. #define CONFIG_ENV_OVERWRITE
  17. #ifndef __ASSEMBLY__
  18. extern unsigned long get_clock_freq(void);
  19. #endif
  20. /* Replace a call to get_clock_freq (after it is implemented)*/
  21. #define CONFIG_SYS_CLK_FREQ 66666666
  22. #define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ
  23. #ifdef CONFIG_ATM
  24. #define CONFIG_PQ_MDS_PIB
  25. #define CONFIG_PQ_MDS_PIB_ATM
  26. #endif
  27. /*
  28. * These can be toggled for performance analysis, otherwise use default.
  29. */
  30. #define CONFIG_L2_CACHE /* toggle L2 cache */
  31. #define CONFIG_BTB /* toggle branch predition */
  32. #ifndef CONFIG_SYS_MONITOR_BASE
  33. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  34. #endif
  35. /*
  36. * Only possible on E500 Version 2 or newer cores.
  37. */
  38. #define CONFIG_ENABLE_36BIT_PHYS 1
  39. #define CONFIG_HWCONFIG
  40. #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
  41. #define CONFIG_SYS_MEMTEST_END 0x00400000
  42. /*
  43. * Config the L2 Cache as L2 SRAM
  44. */
  45. #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
  46. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  47. #define CONFIG_SYS_L2_SIZE (512 << 10)
  48. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  49. #define CONFIG_SYS_CCSRBAR 0xe0000000
  50. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  51. #if defined(CONFIG_NAND_SPL)
  52. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  53. #endif
  54. /* DDR Setup */
  55. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
  56. #define CONFIG_DDR_SPD
  57. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
  58. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  59. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  60. /* DDR is system memory*/
  61. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  62. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  63. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  64. /* I2C addresses of SPD EEPROMs */
  65. #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
  66. /* These are used when DDR doesn't use SPD. */
  67. #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */
  68. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
  69. #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
  70. #define CONFIG_SYS_DDR_TIMING_3 0x00020000
  71. #define CONFIG_SYS_DDR_TIMING_0 0x00330004
  72. #define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644
  73. #define CONFIG_SYS_DDR_TIMING_2 0x002888D0
  74. #define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000
  75. #define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040
  76. #define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521
  77. #define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000
  78. #define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000
  79. #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
  80. #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000
  81. #define CONFIG_SYS_DDR_TIMING_4 0x00220001
  82. #define CONFIG_SYS_DDR_TIMING_5 0x03402400
  83. #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
  84. #define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604
  85. #define CONFIG_SYS_DDR_CDR_1 0x80040000
  86. #define CONFIG_SYS_DDR_CDR_2 0x00000000
  87. #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
  88. #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
  89. #define CONFIG_SYS_DDR_CONTROL 0xc7000000 /* Type = DDR3 */
  90. #define CONFIG_SYS_DDR_CONTROL2 0x24400000
  91. #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
  92. #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
  93. #define CONFIG_SYS_DDR_SBE 0x00010000
  94. #undef CONFIG_CLOCKS_IN_MHZ
  95. /*
  96. * Local Bus Definitions
  97. */
  98. #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */
  99. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  100. #define CONFIG_SYS_BCSR_BASE 0xf8000000
  101. #define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE
  102. /*Chip select 0 - Flash*/
  103. #define CONFIG_FLASH_BR_PRELIM 0xfe000801
  104. #define CONFIG_FLASH_OR_PRELIM 0xfe000ff7
  105. /*Chip select 1 - BCSR*/
  106. #define CONFIG_SYS_BR1_PRELIM 0xf8000801
  107. #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7
  108. /*Chip select 4 - PIB*/
  109. #define CONFIG_SYS_BR4_PRELIM 0xf8008801
  110. #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7
  111. /*Chip select 5 - PIB*/
  112. #define CONFIG_SYS_BR5_PRELIM 0xf8010801
  113. #define CONFIG_SYS_OR5_PRELIM 0xffffe9f7
  114. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  115. #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
  116. #undef CONFIG_SYS_FLASH_CHECKSUM
  117. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  118. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  119. #undef CONFIG_SYS_RAMBOOT
  120. #define CONFIG_SYS_FLASH_EMPTY_INFO
  121. /* Chip select 3 - NAND */
  122. #ifndef CONFIG_NAND_SPL
  123. #define CONFIG_SYS_NAND_BASE 0xFC000000
  124. #else
  125. #define CONFIG_SYS_NAND_BASE 0xFFF00000
  126. #endif
  127. /* NAND boot: 4K NAND loader config */
  128. #define CONFIG_SYS_NAND_SPL_SIZE 0x1000
  129. #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
  130. #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
  131. #define CONFIG_SYS_NAND_U_BOOT_START \
  132. (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
  133. #define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
  134. #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
  135. #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
  136. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  137. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, }
  138. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  139. #define CONFIG_NAND_FSL_ELBC 1
  140. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  141. #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
  142. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  143. | BR_PS_8 /* Port Size = 8 bit */ \
  144. | BR_MS_FCM /* MSEL = FCM */ \
  145. | BR_V) /* valid */
  146. #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
  147. | OR_FCM_CSCT \
  148. | OR_FCM_CST \
  149. | OR_FCM_CHT \
  150. | OR_FCM_SCY_1 \
  151. | OR_FCM_TRLX \
  152. | OR_FCM_EHTR)
  153. #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
  154. #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
  155. #define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
  156. #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  157. #define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */
  158. #define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */
  159. #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
  160. #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
  161. #define CONFIG_SYS_INIT_RAM_LOCK 1
  162. #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
  163. #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
  164. #define CONFIG_SYS_GBL_DATA_OFFSET \
  165. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  166. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  167. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
  168. #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
  169. /* Serial Port */
  170. #define CONFIG_SYS_NS16550_SERIAL
  171. #define CONFIG_SYS_NS16550_REG_SIZE 1
  172. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  173. #ifdef CONFIG_NAND_SPL
  174. #define CONFIG_NS16550_MIN_FUNCTIONS
  175. #endif
  176. #define CONFIG_SYS_BAUDRATE_TABLE \
  177. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  178. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  179. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  180. /*
  181. * I2C
  182. */
  183. #define CONFIG_SYS_I2C
  184. #define CONFIG_SYS_I2C_FSL
  185. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  186. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  187. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  188. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  189. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  190. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  191. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
  192. /*
  193. * I2C2 EEPROM
  194. */
  195. #define CONFIG_ID_EEPROM
  196. #ifdef CONFIG_ID_EEPROM
  197. #define CONFIG_SYS_I2C_EEPROM_NXID
  198. #endif
  199. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
  200. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  201. #define CONFIG_SYS_EEPROM_BUS_NUM 1
  202. #define PLPPAR1_I2C_BIT_MASK 0x0000000F
  203. #define PLPPAR1_I2C2_VAL 0x00000000
  204. #define PLPPAR1_ESDHC_VAL 0x0000000A
  205. #define PLPDIR1_I2C_BIT_MASK 0x0000000F
  206. #define PLPDIR1_I2C2_VAL 0x0000000F
  207. #define PLPDIR1_ESDHC_VAL 0x00000006
  208. #define PLPPAR1_UART0_BIT_MASK 0x00000fc0
  209. #define PLPPAR1_ESDHC_4BITS_VAL 0x00000a80
  210. #define PLPDIR1_UART0_BIT_MASK 0x00000fc0
  211. #define PLPDIR1_ESDHC_4BITS_VAL 0x00000a80
  212. /*
  213. * General PCI
  214. * Memory Addresses are mapped 1-1. I/O is mapped from 0
  215. */
  216. #define CONFIG_SYS_PCIE1_NAME "Slot"
  217. #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
  218. #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
  219. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
  220. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  221. #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
  222. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  223. #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
  224. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
  225. #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000
  226. #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000
  227. #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS
  228. #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
  229. #ifdef CONFIG_QE
  230. /*
  231. * QE UEC ethernet configuration
  232. */
  233. #define CONFIG_SYS_UCC_RGMII_MODE /* Set UCC work at RGMII by default */
  234. #undef CONFIG_SYS_UCC_RMII_MODE /* Set UCC work at RMII mode */
  235. #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
  236. #define CONFIG_UEC_ETH
  237. #define CONFIG_ETHPRIME "UEC0"
  238. #define CONFIG_PHY_MODE_NEED_CHANGE
  239. #define CONFIG_UEC_ETH1 /* GETH1 */
  240. #define CONFIG_HAS_ETH0
  241. #ifdef CONFIG_UEC_ETH1
  242. #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
  243. #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
  244. #if defined(CONFIG_SYS_UCC_RGMII_MODE)
  245. #define CONFIG_SYS_UEC1_TX_CLK QE_CLK12
  246. #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
  247. #define CONFIG_SYS_UEC1_PHY_ADDR 7
  248. #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
  249. #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
  250. #elif defined(CONFIG_SYS_UCC_RMII_MODE)
  251. #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */
  252. #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
  253. #define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */
  254. #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
  255. #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
  256. #endif /* CONFIG_SYS_UCC_RGMII_MODE */
  257. #endif /* CONFIG_UEC_ETH1 */
  258. #define CONFIG_UEC_ETH2 /* GETH2 */
  259. #define CONFIG_HAS_ETH1
  260. #ifdef CONFIG_UEC_ETH2
  261. #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
  262. #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
  263. #if defined(CONFIG_SYS_UCC_RGMII_MODE)
  264. #define CONFIG_SYS_UEC2_TX_CLK QE_CLK17
  265. #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
  266. #define CONFIG_SYS_UEC2_PHY_ADDR 1
  267. #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
  268. #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
  269. #elif defined(CONFIG_SYS_UCC_RMII_MODE)
  270. #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */
  271. #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
  272. #define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */
  273. #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
  274. #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
  275. #endif /* CONFIG_SYS_UCC_RGMII_MODE */
  276. #endif /* CONFIG_UEC_ETH2 */
  277. #define CONFIG_UEC_ETH3 /* GETH3 */
  278. #define CONFIG_HAS_ETH2
  279. #ifdef CONFIG_UEC_ETH3
  280. #define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */
  281. #define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE
  282. #if defined(CONFIG_SYS_UCC_RGMII_MODE)
  283. #define CONFIG_SYS_UEC3_TX_CLK QE_CLK12
  284. #define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH
  285. #define CONFIG_SYS_UEC3_PHY_ADDR 2
  286. #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
  287. #define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000
  288. #elif defined(CONFIG_SYS_UCC_RMII_MODE)
  289. #define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */
  290. #define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH
  291. #define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */
  292. #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
  293. #define CONFIG_SYS_UEC3_INTERFACE_SPEED 100
  294. #endif /* CONFIG_SYS_UCC_RGMII_MODE */
  295. #endif /* CONFIG_UEC_ETH3 */
  296. #define CONFIG_UEC_ETH4 /* GETH4 */
  297. #define CONFIG_HAS_ETH3
  298. #ifdef CONFIG_UEC_ETH4
  299. #define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */
  300. #define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE
  301. #if defined(CONFIG_SYS_UCC_RGMII_MODE)
  302. #define CONFIG_SYS_UEC4_TX_CLK QE_CLK17
  303. #define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH
  304. #define CONFIG_SYS_UEC4_PHY_ADDR 3
  305. #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
  306. #define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000
  307. #elif defined(CONFIG_SYS_UCC_RMII_MODE)
  308. #define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */
  309. #define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH
  310. #define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */
  311. #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
  312. #define CONFIG_SYS_UEC4_INTERFACE_SPEED 100
  313. #endif /* CONFIG_SYS_UCC_RGMII_MODE */
  314. #endif /* CONFIG_UEC_ETH4 */
  315. #undef CONFIG_UEC_ETH6 /* GETH6 */
  316. #define CONFIG_HAS_ETH5
  317. #ifdef CONFIG_UEC_ETH6
  318. #define CONFIG_SYS_UEC6_UCC_NUM 5 /* UCC6 */
  319. #define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE
  320. #define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE
  321. #define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH
  322. #define CONFIG_SYS_UEC6_PHY_ADDR 4
  323. #define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
  324. #define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000
  325. #endif /* CONFIG_UEC_ETH6 */
  326. #undef CONFIG_UEC_ETH8 /* GETH8 */
  327. #define CONFIG_HAS_ETH7
  328. #ifdef CONFIG_UEC_ETH8
  329. #define CONFIG_SYS_UEC8_UCC_NUM 7 /* UCC8 */
  330. #define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE
  331. #define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE
  332. #define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH
  333. #define CONFIG_SYS_UEC8_PHY_ADDR 6
  334. #define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
  335. #define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000
  336. #endif /* CONFIG_UEC_ETH8 */
  337. #endif /* CONFIG_QE */
  338. #if defined(CONFIG_PCI)
  339. #undef CONFIG_EEPRO100
  340. #undef CONFIG_TULIP
  341. #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  342. #endif /* CONFIG_PCI */
  343. /*
  344. * Environment
  345. */
  346. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  347. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  348. /* QE microcode/firmware address */
  349. #define CONFIG_SYS_QE_FW_ADDR 0xfff00000
  350. /*
  351. * BOOTP options
  352. */
  353. #define CONFIG_BOOTP_BOOTFILESIZE
  354. #undef CONFIG_WATCHDOG /* watchdog disabled */
  355. #ifdef CONFIG_MMC
  356. #define CONFIG_FSL_ESDHC_PIN_MUX
  357. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  358. #endif
  359. /*
  360. * Miscellaneous configurable options
  361. */
  362. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  363. #if defined(CONFIG_CMD_KGDB)
  364. #define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */
  365. #else
  366. #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
  367. #endif
  368. #define CONFIG_SYS_MAXARGS 32 /* max number of command args */
  369. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  370. /* Boot Argument Buffer Size */
  371. /*
  372. * For booting Linux, the board info and command line data
  373. * have to be in the first 64 MB of memory, since this is
  374. * the maximum mapped by the Linux kernel during initialization.
  375. */
  376. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
  377. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  378. #if defined(CONFIG_CMD_KGDB)
  379. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  380. #endif
  381. /*
  382. * Environment Configuration
  383. */
  384. #define CONFIG_HOSTNAME "mpc8569mds"
  385. #define CONFIG_ROOTPATH "/nfsroot"
  386. #define CONFIG_BOOTFILE "your.uImage"
  387. #define CONFIG_SERVERIP 192.168.1.1
  388. #define CONFIG_GATEWAYIP 192.168.1.1
  389. #define CONFIG_NETMASK 255.255.255.0
  390. #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
  391. #define CONFIG_EXTRA_ENV_SETTINGS \
  392. "netdev=eth0\0" \
  393. "consoledev=ttyS0\0" \
  394. "ramdiskaddr=600000\0" \
  395. "ramdiskfile=your.ramdisk.u-boot\0" \
  396. "fdtaddr=400000\0" \
  397. "fdtfile=your.fdt.dtb\0" \
  398. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  399. "nfsroot=$serverip:$rootpath " \
  400. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  401. "console=$consoledev,$baudrate $othbootargs\0" \
  402. "ramargs=setenv bootargs root=/dev/ram rw " \
  403. "console=$consoledev,$baudrate $othbootargs\0" \
  404. #define CONFIG_NFSBOOTCOMMAND \
  405. "run nfsargs;" \
  406. "tftp $loadaddr $bootfile;" \
  407. "tftp $fdtaddr $fdtfile;" \
  408. "bootm $loadaddr - $fdtaddr"
  409. #define CONFIG_RAMBOOTCOMMAND \
  410. "run ramargs;" \
  411. "tftp $ramdiskaddr $ramdiskfile;" \
  412. "tftp $loadaddr $bootfile;" \
  413. "bootm $loadaddr $ramdiskaddr"
  414. #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
  415. #endif /* __CONFIG_H */