MPC8568MDS.h 13 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2004-2007, 2010-2011 Freescale Semiconductor.
  4. */
  5. /*
  6. * mpc8568mds board configuration file
  7. */
  8. #ifndef __CONFIG_H
  9. #define __CONFIG_H
  10. #define CONFIG_SYS_SRIO
  11. #define CONFIG_SRIO1 /* SRIO port 1 */
  12. #define CONFIG_PCI1 1 /* PCI controller */
  13. #define CONFIG_PCIE1 1 /* PCIE controller */
  14. #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
  15. #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
  16. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  17. #define CONFIG_ENV_OVERWRITE
  18. #ifndef __ASSEMBLY__
  19. extern unsigned long get_clock_freq(void);
  20. #endif /*Replace a call to get_clock_freq (after it is implemented)*/
  21. #define CONFIG_SYS_CLK_FREQ 66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */
  22. /*
  23. * These can be toggled for performance analysis, otherwise use default.
  24. */
  25. #define CONFIG_L2_CACHE /* toggle L2 cache */
  26. #define CONFIG_BTB /* toggle branch predition */
  27. /*
  28. * Only possible on E500 Version 2 or newer cores.
  29. */
  30. #define CONFIG_ENABLE_36BIT_PHYS 1
  31. #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
  32. #define CONFIG_SYS_MEMTEST_END 0x00400000
  33. #define CONFIG_SYS_CCSRBAR 0xe0000000
  34. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  35. /* DDR Setup */
  36. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
  37. #define CONFIG_DDR_SPD
  38. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
  39. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  40. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
  41. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  42. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  43. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  44. /* I2C addresses of SPD EEPROMs */
  45. #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
  46. /* Make sure required options are set */
  47. #ifndef CONFIG_SPD_EEPROM
  48. #error ("CONFIG_SPD_EEPROM is required")
  49. #endif
  50. #undef CONFIG_CLOCKS_IN_MHZ
  51. /*
  52. * Local Bus Definitions
  53. */
  54. /*
  55. * FLASH on the Local Bus
  56. * Two banks, 8M each, using the CFI driver.
  57. * Boot from BR0/OR0 bank at 0xff00_0000
  58. * Alternate BR1/OR1 bank at 0xff80_0000
  59. *
  60. * BR0, BR1:
  61. * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
  62. * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
  63. * Port Size = 16 bits = BRx[19:20] = 10
  64. * Use GPCM = BRx[24:26] = 000
  65. * Valid = BRx[31] = 1
  66. *
  67. * 0 4 8 12 16 20 24 28
  68. * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
  69. * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
  70. *
  71. * OR0, OR1:
  72. * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
  73. * Reserved ORx[17:18] = 11, confusion here?
  74. * CSNT = ORx[20] = 1
  75. * ACS = half cycle delay = ORx[21:22] = 11
  76. * SCY = 6 = ORx[24:27] = 0110
  77. * TRLX = use relaxed timing = ORx[29] = 1
  78. * EAD = use external address latch delay = OR[31] = 1
  79. *
  80. * 0 4 8 12 16 20 24 28
  81. * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
  82. */
  83. #define CONFIG_SYS_BCSR_BASE 0xf8000000
  84. #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */
  85. /*Chip select 0 - Flash*/
  86. #define CONFIG_SYS_BR0_PRELIM 0xfe001001
  87. #define CONFIG_SYS_OR0_PRELIM 0xfe006ff7
  88. /*Chip slelect 1 - BCSR*/
  89. #define CONFIG_SYS_BR1_PRELIM 0xf8000801
  90. #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7
  91. /*#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} */
  92. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  93. #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
  94. #undef CONFIG_SYS_FLASH_CHECKSUM
  95. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  96. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  97. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  98. #define CONFIG_SYS_FLASH_EMPTY_INFO
  99. /*
  100. * SDRAM on the LocalBus
  101. */
  102. #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
  103. #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
  104. /*Chip select 2 - SDRAM*/
  105. #define CONFIG_SYS_BR2_PRELIM 0xf0001861
  106. #define CONFIG_SYS_OR2_PRELIM 0xfc006901
  107. #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
  108. #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
  109. #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
  110. #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
  111. /*
  112. * Common settings for all Local Bus SDRAM commands.
  113. * At run time, either BSMA1516 (for CPU 1.1)
  114. * or BSMA1617 (for CPU 1.0) (old)
  115. * is OR'ed in too.
  116. */
  117. #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
  118. | LSDMR_PRETOACT7 \
  119. | LSDMR_ACTTORW7 \
  120. | LSDMR_BL8 \
  121. | LSDMR_WRC4 \
  122. | LSDMR_CL3 \
  123. | LSDMR_RFEN \
  124. )
  125. /*
  126. * The bcsr registers are connected to CS3 on MDS.
  127. * The new memory map places bcsr at 0xf8000000.
  128. *
  129. * For BR3, need:
  130. * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
  131. * port-size = 8-bits = BR[19:20] = 01
  132. * no parity checking = BR[21:22] = 00
  133. * GPMC for MSEL = BR[24:26] = 000
  134. * Valid = BR[31] = 1
  135. *
  136. * 0 4 8 12 16 20 24 28
  137. * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
  138. *
  139. * For OR3, need:
  140. * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
  141. * disable buffer ctrl OR[19] = 0
  142. * CSNT OR[20] = 1
  143. * ACS OR[21:22] = 11
  144. * XACS OR[23] = 1
  145. * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
  146. * SETA OR[28] = 0
  147. * TRLX OR[29] = 1
  148. * EHTR OR[30] = 1
  149. * EAD extra time OR[31] = 1
  150. *
  151. * 0 4 8 12 16 20 24 28
  152. * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
  153. */
  154. #define CONFIG_SYS_BCSR (0xf8000000)
  155. /*Chip slelect 4 - PIB*/
  156. #define CONFIG_SYS_BR4_PRELIM 0xf8008801
  157. #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7
  158. /*Chip select 5 - PIB*/
  159. #define CONFIG_SYS_BR5_PRELIM 0xf8010801
  160. #define CONFIG_SYS_OR5_PRELIM 0xffff69f7
  161. #define CONFIG_SYS_INIT_RAM_LOCK 1
  162. #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
  163. #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
  164. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  165. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  166. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
  167. #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
  168. /* Serial Port */
  169. #define CONFIG_SYS_NS16550_SERIAL
  170. #define CONFIG_SYS_NS16550_REG_SIZE 1
  171. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  172. #define CONFIG_SYS_BAUDRATE_TABLE \
  173. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  174. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  175. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  176. /*
  177. * I2C
  178. */
  179. #define CONFIG_SYS_I2C
  180. #define CONFIG_SYS_I2C_FSL
  181. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  182. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  183. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  184. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  185. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  186. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  187. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
  188. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
  189. /*
  190. * General PCI
  191. * Memory Addresses are mapped 1-1. I/O is mapped from 0
  192. */
  193. #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
  194. #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
  195. #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
  196. #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
  197. #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
  198. #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
  199. #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
  200. #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */
  201. #define CONFIG_SYS_PCIE1_NAME "Slot"
  202. #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
  203. #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
  204. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
  205. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  206. #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
  207. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  208. #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
  209. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
  210. #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000
  211. #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000
  212. #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS
  213. #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
  214. #ifdef CONFIG_QE
  215. /*
  216. * QE UEC ethernet configuration
  217. */
  218. #define CONFIG_UEC_ETH
  219. #ifndef CONFIG_TSEC_ENET
  220. #define CONFIG_ETHPRIME "UEC0"
  221. #endif
  222. #define CONFIG_PHY_MODE_NEED_CHANGE
  223. #define CONFIG_eTSEC_MDIO_BUS
  224. #ifdef CONFIG_eTSEC_MDIO_BUS
  225. #define CONFIG_MIIM_ADDRESS 0xE0024520
  226. #endif
  227. #define CONFIG_UEC_ETH1 /* GETH1 */
  228. #ifdef CONFIG_UEC_ETH1
  229. #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
  230. #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
  231. #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16
  232. #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
  233. #define CONFIG_SYS_UEC1_PHY_ADDR 7
  234. #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
  235. #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
  236. #endif
  237. #define CONFIG_UEC_ETH2 /* GETH2 */
  238. #ifdef CONFIG_UEC_ETH2
  239. #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
  240. #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
  241. #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16
  242. #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
  243. #define CONFIG_SYS_UEC2_PHY_ADDR 1
  244. #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
  245. #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
  246. #endif
  247. #endif /* CONFIG_QE */
  248. #if defined(CONFIG_PCI)
  249. #undef CONFIG_EEPRO100
  250. #undef CONFIG_TULIP
  251. #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  252. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
  253. #endif /* CONFIG_PCI */
  254. #if defined(CONFIG_TSEC_ENET)
  255. #define CONFIG_TSEC1 1
  256. #define CONFIG_TSEC1_NAME "eTSEC0"
  257. #define CONFIG_TSEC2 1
  258. #define CONFIG_TSEC2_NAME "eTSEC1"
  259. #define TSEC1_PHY_ADDR 2
  260. #define TSEC2_PHY_ADDR 3
  261. #define TSEC1_PHYIDX 0
  262. #define TSEC2_PHYIDX 0
  263. #define TSEC1_FLAGS TSEC_GIGABIT
  264. #define TSEC2_FLAGS TSEC_GIGABIT
  265. /* Options are: eTSEC[0-1] */
  266. #define CONFIG_ETHPRIME "eTSEC0"
  267. #endif /* CONFIG_TSEC_ENET */
  268. /*
  269. * Environment
  270. */
  271. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  272. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  273. /*
  274. * BOOTP options
  275. */
  276. #define CONFIG_BOOTP_BOOTFILESIZE
  277. #undef CONFIG_WATCHDOG /* watchdog disabled */
  278. /*
  279. * Miscellaneous configurable options
  280. */
  281. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  282. /*
  283. * For booting Linux, the board info and command line data
  284. * have to be in the first 64 MB of memory, since this is
  285. * the maximum mapped by the Linux kernel during initialization.
  286. */
  287. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
  288. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  289. #if defined(CONFIG_CMD_KGDB)
  290. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  291. #endif
  292. /*
  293. * Environment Configuration
  294. */
  295. /* The mac addresses for all ethernet interface */
  296. #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH)
  297. #define CONFIG_HAS_ETH0
  298. #define CONFIG_HAS_ETH1
  299. #define CONFIG_HAS_ETH2
  300. #define CONFIG_HAS_ETH3
  301. #endif
  302. #define CONFIG_IPADDR 192.168.1.253
  303. #define CONFIG_HOSTNAME "unknown"
  304. #define CONFIG_ROOTPATH "/nfsroot"
  305. #define CONFIG_BOOTFILE "your.uImage"
  306. #define CONFIG_SERVERIP 192.168.1.1
  307. #define CONFIG_GATEWAYIP 192.168.1.1
  308. #define CONFIG_NETMASK 255.255.255.0
  309. #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
  310. #define CONFIG_EXTRA_ENV_SETTINGS \
  311. "netdev=eth0\0" \
  312. "consoledev=ttyS0\0" \
  313. "ramdiskaddr=600000\0" \
  314. "ramdiskfile=your.ramdisk.u-boot\0" \
  315. "fdtaddr=400000\0" \
  316. "fdtfile=your.fdt.dtb\0" \
  317. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  318. "nfsroot=$serverip:$rootpath " \
  319. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  320. "console=$consoledev,$baudrate $othbootargs\0" \
  321. "ramargs=setenv bootargs root=/dev/ram rw " \
  322. "console=$consoledev,$baudrate $othbootargs\0" \
  323. #define CONFIG_NFSBOOTCOMMAND \
  324. "run nfsargs;" \
  325. "tftp $loadaddr $bootfile;" \
  326. "tftp $fdtaddr $fdtfile;" \
  327. "bootm $loadaddr - $fdtaddr"
  328. #define CONFIG_RAMBOOTCOMMAND \
  329. "run ramargs;" \
  330. "tftp $ramdiskaddr $ramdiskfile;" \
  331. "tftp $loadaddr $bootfile;" \
  332. "bootm $loadaddr $ramdiskaddr"
  333. #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
  334. #endif /* __CONFIG_H */