MPC8560ADS.h 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2004, 2011 Freescale Semiconductor.
  4. * (C) Copyright 2002,2003 Motorola,Inc.
  5. * Xianghua Xiao <X.Xiao@motorola.com>
  6. */
  7. /*
  8. * mpc8560ads board configuration file
  9. *
  10. * Please refer to doc/README.mpc85xx for more info.
  11. *
  12. * Make sure you change the MAC address and other network params first,
  13. * search for CONFIG_SERVERIP, etc. in this file.
  14. */
  15. #ifndef __CONFIG_H
  16. #define __CONFIG_H
  17. /* High Level Configuration Options */
  18. #define CONFIG_CPM2 1 /* has CPM2 */
  19. /*
  20. * default CCARBAR is at 0xff700000
  21. * assume U-Boot is less than 0.5MB
  22. */
  23. #define CONFIG_PCI_INDIRECT_BRIDGE
  24. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  25. #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
  26. #define CONFIG_ENV_OVERWRITE
  27. #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
  28. /*
  29. * sysclk for MPC85xx
  30. *
  31. * Two valid values are:
  32. * 33000000
  33. * 66000000
  34. *
  35. * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
  36. * is likely the desired value here, so that is now the default.
  37. * The board, however, can run at 66MHz. In any event, this value
  38. * must match the settings of some switches. Details can be found
  39. * in the README.mpc85xxads.
  40. */
  41. #ifndef CONFIG_SYS_CLK_FREQ
  42. #define CONFIG_SYS_CLK_FREQ 33000000
  43. #endif
  44. /*
  45. * These can be toggled for performance analysis, otherwise use default.
  46. */
  47. #define CONFIG_L2_CACHE /* toggle L2 cache */
  48. #define CONFIG_BTB /* toggle branch predition */
  49. #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
  50. #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
  51. #define CONFIG_SYS_MEMTEST_END 0x00400000
  52. #define CONFIG_SYS_CCSRBAR 0xe0000000
  53. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  54. /* DDR Setup */
  55. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
  56. #define CONFIG_DDR_SPD
  57. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  58. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
  59. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  60. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  61. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  62. /* I2C addresses of SPD EEPROMs */
  63. #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
  64. /* These are used when DDR doesn't use SPD. */
  65. #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */
  66. #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
  67. #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
  68. #define CONFIG_SYS_DDR_TIMING_1 0x37344321
  69. #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
  70. #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
  71. #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
  72. #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
  73. /*
  74. * SDRAM on the Local Bus
  75. */
  76. #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
  77. #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
  78. #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
  79. #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
  80. #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
  81. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  82. #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
  83. #undef CONFIG_SYS_FLASH_CHECKSUM
  84. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  85. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  86. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  87. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  88. #define CONFIG_SYS_RAMBOOT
  89. #else
  90. #undef CONFIG_SYS_RAMBOOT
  91. #endif
  92. #define CONFIG_SYS_FLASH_EMPTY_INFO
  93. #undef CONFIG_CLOCKS_IN_MHZ
  94. /*
  95. * Local Bus Definitions
  96. */
  97. /*
  98. * Base Register 2 and Option Register 2 configure SDRAM.
  99. * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
  100. *
  101. * For BR2, need:
  102. * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
  103. * port-size = 32-bits = BR2[19:20] = 11
  104. * no parity checking = BR2[21:22] = 00
  105. * SDRAM for MSEL = BR2[24:26] = 011
  106. * Valid = BR[31] = 1
  107. *
  108. * 0 4 8 12 16 20 24 28
  109. * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
  110. *
  111. * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
  112. * FIXME: the top 17 bits of BR2.
  113. */
  114. #define CONFIG_SYS_BR2_PRELIM 0xf0001861
  115. /*
  116. * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
  117. *
  118. * For OR2, need:
  119. * 64MB mask for AM, OR2[0:7] = 1111 1100
  120. * XAM, OR2[17:18] = 11
  121. * 9 columns OR2[19-21] = 010
  122. * 13 rows OR2[23-25] = 100
  123. * EAD set for extra time OR[31] = 1
  124. *
  125. * 0 4 8 12 16 20 24 28
  126. * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
  127. */
  128. #define CONFIG_SYS_OR2_PRELIM 0xfc006901
  129. #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
  130. #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
  131. #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
  132. #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
  133. #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \
  134. | LSDMR_RFCR5 \
  135. | LSDMR_PRETOACT3 \
  136. | LSDMR_ACTTORW3 \
  137. | LSDMR_BL8 \
  138. | LSDMR_WRC2 \
  139. | LSDMR_CL3 \
  140. | LSDMR_RFEN \
  141. )
  142. /*
  143. * SDRAM Controller configuration sequence.
  144. */
  145. #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
  146. #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
  147. #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
  148. #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
  149. #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
  150. /*
  151. * 32KB, 8-bit wide for ADS config reg
  152. */
  153. #define CONFIG_SYS_BR4_PRELIM 0xf8000801
  154. #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
  155. #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
  156. #define CONFIG_SYS_INIT_RAM_LOCK 1
  157. #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
  158. #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
  159. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  160. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  161. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
  162. #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
  163. /* Serial Port */
  164. #define CONFIG_CONS_ON_SCC /* define if console on SCC */
  165. #undef CONFIG_CONS_NONE /* define if console on something else */
  166. #define CONFIG_SYS_BAUDRATE_TABLE \
  167. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  168. /*
  169. * I2C
  170. */
  171. #define CONFIG_SYS_I2C
  172. #define CONFIG_SYS_I2C_FSL
  173. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  174. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  175. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  176. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
  177. /* RapidIO MMU */
  178. #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */
  179. #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */
  180. #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
  181. #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
  182. /*
  183. * General PCI
  184. * Memory space is mapped 1-1, but I/O space must start from 0.
  185. */
  186. #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
  187. #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
  188. #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
  189. #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
  190. #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
  191. #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
  192. #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
  193. #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
  194. #if defined(CONFIG_PCI)
  195. #undef CONFIG_EEPRO100
  196. #undef CONFIG_TULIP
  197. #if !defined(CONFIG_PCI_PNP)
  198. #define PCI_ENET0_IOADDR 0xe0000000
  199. #define PCI_ENET0_MEMADDR 0xe0000000
  200. #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
  201. #endif
  202. #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  203. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
  204. #endif /* CONFIG_PCI */
  205. #ifdef CONFIG_TSEC_ENET
  206. #define CONFIG_TSEC1 1
  207. #define CONFIG_TSEC1_NAME "TSEC0"
  208. #define CONFIG_TSEC2 1
  209. #define CONFIG_TSEC2_NAME "TSEC1"
  210. #define TSEC1_PHY_ADDR 0
  211. #define TSEC2_PHY_ADDR 1
  212. #define TSEC1_PHYIDX 0
  213. #define TSEC2_PHYIDX 0
  214. #define TSEC1_FLAGS TSEC_GIGABIT
  215. #define TSEC2_FLAGS TSEC_GIGABIT
  216. /* Options are: TSEC[0-1] */
  217. #define CONFIG_ETHPRIME "TSEC0"
  218. #endif /* CONFIG_TSEC_ENET */
  219. #ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */
  220. #undef CONFIG_ETHER_NONE /* define if ether on something else */
  221. #define CONFIG_ETHER_INDEX 2 /* which channel for ether */
  222. #if (CONFIG_ETHER_INDEX == 2)
  223. /*
  224. * - Rx-CLK is CLK13
  225. * - Tx-CLK is CLK14
  226. * - Select bus for bd/buffers
  227. * - Full duplex
  228. */
  229. #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
  230. #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
  231. #define CONFIG_SYS_CPMFCR_RAMTYPE 0
  232. #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
  233. #define FETH2_RST 0x01
  234. #elif (CONFIG_ETHER_INDEX == 3)
  235. /* need more definitions here for FE3 */
  236. #define FETH3_RST 0x80
  237. #endif /* CONFIG_ETHER_INDEX */
  238. #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
  239. /*
  240. * GPIO pins used for bit-banged MII communications
  241. */
  242. #define MDIO_PORT 2 /* Port C */
  243. #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
  244. (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
  245. #define MDC_DECLARE MDIO_DECLARE
  246. #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
  247. #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
  248. #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
  249. #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
  250. else iop->pdat &= ~0x00400000
  251. #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
  252. else iop->pdat &= ~0x00200000
  253. #define MIIDELAY udelay(1)
  254. #endif
  255. /*
  256. * Environment
  257. */
  258. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  259. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  260. /*
  261. * BOOTP options
  262. */
  263. #define CONFIG_BOOTP_BOOTFILESIZE
  264. #undef CONFIG_WATCHDOG /* watchdog disabled */
  265. /*
  266. * Miscellaneous configurable options
  267. */
  268. #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
  269. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  270. /*
  271. * For booting Linux, the board info and command line data
  272. * have to be in the first 64 MB of memory, since this is
  273. * the maximum mapped by the Linux kernel during initialization.
  274. */
  275. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
  276. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  277. #if defined(CONFIG_CMD_KGDB)
  278. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  279. #endif
  280. /*
  281. * Environment Configuration
  282. */
  283. #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
  284. #define CONFIG_HAS_ETH0
  285. #define CONFIG_HAS_ETH1
  286. #define CONFIG_HAS_ETH2
  287. #define CONFIG_HAS_ETH3
  288. #endif
  289. #define CONFIG_IPADDR 192.168.1.253
  290. #define CONFIG_HOSTNAME "unknown"
  291. #define CONFIG_ROOTPATH "/nfsroot"
  292. #define CONFIG_BOOTFILE "your.uImage"
  293. #define CONFIG_SERVERIP 192.168.1.1
  294. #define CONFIG_GATEWAYIP 192.168.1.1
  295. #define CONFIG_NETMASK 255.255.255.0
  296. #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
  297. #define CONFIG_EXTRA_ENV_SETTINGS \
  298. "netdev=eth0\0" \
  299. "consoledev=ttyCPM\0" \
  300. "ramdiskaddr=1000000\0" \
  301. "ramdiskfile=your.ramdisk.u-boot\0" \
  302. "fdtaddr=400000\0" \
  303. "fdtfile=mpc8560ads.dtb\0"
  304. #define CONFIG_NFSBOOTCOMMAND \
  305. "setenv bootargs root=/dev/nfs rw " \
  306. "nfsroot=$serverip:$rootpath " \
  307. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  308. "console=$consoledev,$baudrate $othbootargs;" \
  309. "tftp $loadaddr $bootfile;" \
  310. "tftp $fdtaddr $fdtfile;" \
  311. "bootm $loadaddr - $fdtaddr"
  312. #define CONFIG_RAMBOOTCOMMAND \
  313. "setenv bootargs root=/dev/ram rw " \
  314. "console=$consoledev,$baudrate $othbootargs;" \
  315. "tftp $ramdiskaddr $ramdiskfile;" \
  316. "tftp $loadaddr $bootfile;" \
  317. "tftp $fdtaddr $fdtfile;" \
  318. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  319. #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
  320. #endif /* __CONFIG_H */