MPC8544DS.h 13 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc.
  4. */
  5. /*
  6. * mpc8544ds board configuration file
  7. *
  8. */
  9. #ifndef __CONFIG_H
  10. #define __CONFIG_H
  11. #define CONFIG_PCI1 1 /* PCI controller 1 */
  12. #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
  13. #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
  14. #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
  15. #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
  16. #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
  17. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  18. #define CONFIG_ENV_OVERWRITE
  19. #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
  20. #ifndef __ASSEMBLY__
  21. extern unsigned long get_board_sys_clk(unsigned long dummy);
  22. #endif
  23. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
  24. /*
  25. * These can be toggled for performance analysis, otherwise use default.
  26. */
  27. #define CONFIG_L2_CACHE /* toggle L2 cache */
  28. #define CONFIG_BTB /* toggle branch predition */
  29. /*
  30. * Only possible on E500 Version 2 or newer cores.
  31. */
  32. #define CONFIG_ENABLE_36BIT_PHYS 1
  33. #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
  34. #define CONFIG_SYS_MEMTEST_END 0x00400000
  35. #define CONFIG_SYS_CCSRBAR 0xe0000000
  36. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  37. /* DDR Setup */
  38. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
  39. #define CONFIG_DDR_SPD
  40. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
  41. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  42. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  43. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  44. #define CONFIG_VERY_BIG_RAM
  45. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  46. #define CONFIG_CHIP_SELECTS_PER_CTRL 2
  47. /* I2C addresses of SPD EEPROMs */
  48. #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
  49. /* Make sure required options are set */
  50. #ifndef CONFIG_SPD_EEPROM
  51. #error ("CONFIG_SPD_EEPROM is required")
  52. #endif
  53. #undef CONFIG_CLOCKS_IN_MHZ
  54. /*
  55. * Memory map
  56. *
  57. * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
  58. *
  59. * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
  60. *
  61. * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
  62. *
  63. * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
  64. * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
  65. *
  66. * Localbus cacheable
  67. *
  68. * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable
  69. * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0
  70. *
  71. * Localbus non-cacheable
  72. *
  73. * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable
  74. * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
  75. * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
  76. *
  77. */
  78. /*
  79. * Local Bus Definitions
  80. */
  81. #define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* boot TLB */
  82. #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */
  83. #define CONFIG_SYS_BR0_PRELIM 0xff801001
  84. #define CONFIG_SYS_BR1_PRELIM 0xfe801001
  85. #define CONFIG_SYS_OR0_PRELIM 0xff806e65
  86. #define CONFIG_SYS_OR1_PRELIM 0xff806e65
  87. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
  88. #define CONFIG_SYS_FLASH_QUIET_TEST
  89. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  90. #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
  91. #undef CONFIG_SYS_FLASH_CHECKSUM
  92. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  93. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  94. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  95. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  96. #define CONFIG_SYS_FLASH_EMPTY_INFO
  97. #define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000
  98. #define CONFIG_SYS_BR2_PRELIM 0xf8201001 /* port size 16bit */
  99. #define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/
  100. #define CONFIG_SYS_BR3_PRELIM 0xf8100801 /* port size 8bit */
  101. #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
  102. #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
  103. #define PIXIS_BASE 0xf8100000 /* PIXIS registers */
  104. #define PIXIS_ID 0x0 /* Board ID at offset 0 */
  105. #define PIXIS_VER 0x1 /* Board version at offset 1 */
  106. #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
  107. #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
  108. #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch
  109. * register */
  110. #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
  111. #define PIXIS_VCTL 0x10 /* VELA Control Register */
  112. #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
  113. #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
  114. #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
  115. #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */
  116. #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */
  117. #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
  118. #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
  119. #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
  120. #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
  121. #define PIXIS_VSPEED2 0x1d /* VELA VSpeed 2 */
  122. #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
  123. #define PIXIS_VSPEED2_TSEC1SER 0x2
  124. #define PIXIS_VSPEED2_TSEC3SER 0x1
  125. #define PIXIS_VCFGEN1_TSEC1SER 0x20
  126. #define PIXIS_VCFGEN1_TSEC3SER 0x40
  127. #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER)
  128. #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER)
  129. #define CONFIG_SYS_INIT_RAM_LOCK 1
  130. #define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */
  131. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
  132. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  133. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  134. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
  135. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
  136. /* Serial Port - controlled on board with jumper J8
  137. * open - index 2
  138. * shorted - index 1
  139. */
  140. #define CONFIG_SYS_NS16550_SERIAL
  141. #define CONFIG_SYS_NS16550_REG_SIZE 1
  142. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  143. #define CONFIG_SYS_BAUDRATE_TABLE \
  144. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  145. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  146. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  147. /* I2C */
  148. #define CONFIG_SYS_I2C
  149. #define CONFIG_SYS_I2C_FSL
  150. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  151. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  152. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
  153. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
  154. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  155. /*
  156. * General PCI
  157. * Memory space is mapped 1-1, but I/O space must start from 0.
  158. */
  159. #define CONFIG_SYS_PCIE_VIRT 0x80000000 /* 1G PCIE TLB */
  160. #define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */
  161. #define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */
  162. #define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */
  163. #define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000
  164. #define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000
  165. #define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000
  166. #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
  167. #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
  168. #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
  169. #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
  170. #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
  171. /* controller 2, Slot 1, tgtid 1, Base address 9000 */
  172. #define CONFIG_SYS_PCIE2_NAME "Slot 1"
  173. #define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000
  174. #define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000
  175. #define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000
  176. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
  177. #define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000
  178. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  179. #define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000
  180. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  181. /* controller 1, Slot 2,tgtid 2, Base address a000 */
  182. #define CONFIG_SYS_PCIE1_NAME "Slot 2"
  183. #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
  184. #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
  185. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
  186. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
  187. #define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000
  188. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  189. #define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000
  190. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  191. /* controller 3, direct to uli, tgtid 3, Base address b000 */
  192. #define CONFIG_SYS_PCIE3_NAME "ULI"
  193. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
  194. #define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000
  195. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000
  196. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */
  197. #define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000 /* reuse mem LAW */
  198. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  199. #define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */
  200. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */
  201. #define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000
  202. #define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000
  203. #define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000
  204. #define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */
  205. #if defined(CONFIG_PCI)
  206. /*PCIE video card used*/
  207. #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT
  208. /*PCI video card used*/
  209. /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
  210. /* video */
  211. #if defined(CONFIG_VIDEO)
  212. #define CONFIG_BIOSEMU
  213. #define CONFIG_ATI_RADEON_FB
  214. #define CONFIG_VIDEO_LOGO
  215. #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
  216. #endif
  217. #undef CONFIG_EEPRO100
  218. #undef CONFIG_TULIP
  219. #ifndef CONFIG_PCI_PNP
  220. #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
  221. #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
  222. #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
  223. #endif
  224. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  225. #ifdef CONFIG_SCSI_AHCI
  226. #define CONFIG_SATA_ULI5288
  227. #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
  228. #define CONFIG_SYS_SCSI_MAX_LUN 1
  229. #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
  230. #endif /* CONFIG_SCSI_AHCI */
  231. #endif /* CONFIG_PCI */
  232. #if defined(CONFIG_TSEC_ENET)
  233. #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
  234. #define CONFIG_TSEC1 1
  235. #define CONFIG_TSEC1_NAME "eTSEC1"
  236. #define CONFIG_TSEC3 1
  237. #define CONFIG_TSEC3_NAME "eTSEC3"
  238. #define CONFIG_PIXIS_SGMII_CMD
  239. #define CONFIG_FSL_SGMII_RISER 1
  240. #define SGMII_RISER_PHY_OFFSET 0x1c
  241. #define TSEC1_PHY_ADDR 0
  242. #define TSEC3_PHY_ADDR 1
  243. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  244. #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  245. #define TSEC1_PHYIDX 0
  246. #define TSEC3_PHYIDX 0
  247. #define CONFIG_ETHPRIME "eTSEC1"
  248. #endif /* CONFIG_TSEC_ENET */
  249. /*
  250. * Environment
  251. */
  252. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  253. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  254. /*
  255. * BOOTP options
  256. */
  257. #define CONFIG_BOOTP_BOOTFILESIZE
  258. /*
  259. * USB
  260. */
  261. #ifdef CONFIG_USB_EHCI_HCD
  262. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  263. #define CONFIG_PCI_EHCI_DEVICE 0
  264. #endif
  265. #undef CONFIG_WATCHDOG /* watchdog disabled */
  266. /*
  267. * Miscellaneous configurable options
  268. */
  269. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  270. /*
  271. * For booting Linux, the board info and command line data
  272. * have to be in the first 64 MB of memory, since this is
  273. * the maximum mapped by the Linux kernel during initialization.
  274. */
  275. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
  276. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  277. #if defined(CONFIG_CMD_KGDB)
  278. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  279. #endif
  280. /*
  281. * Environment Configuration
  282. */
  283. /* The mac addresses for all ethernet interface */
  284. #if defined(CONFIG_TSEC_ENET)
  285. #define CONFIG_HAS_ETH0
  286. #define CONFIG_HAS_ETH1
  287. #endif
  288. #define CONFIG_IPADDR 192.168.1.251
  289. #define CONFIG_HOSTNAME "8544ds_unknown"
  290. #define CONFIG_ROOTPATH "/nfs/mpc85xx"
  291. #define CONFIG_BOOTFILE "8544ds/uImage.uboot"
  292. #define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */
  293. #define CONFIG_SERVERIP 192.168.1.1
  294. #define CONFIG_GATEWAYIP 192.168.1.1
  295. #define CONFIG_NETMASK 255.255.0.0
  296. #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
  297. #define CONFIG_EXTRA_ENV_SETTINGS \
  298. "netdev=eth0\0" \
  299. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  300. "tftpflash=tftpboot $loadaddr $uboot; " \
  301. "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
  302. " +$filesize; " \
  303. "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
  304. " +$filesize; " \
  305. "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  306. " $filesize; " \
  307. "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
  308. " +$filesize; " \
  309. "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  310. " $filesize\0" \
  311. "consoledev=ttyS0\0" \
  312. "ramdiskaddr=2000000\0" \
  313. "ramdiskfile=8544ds/ramdisk.uboot\0" \
  314. "fdtaddr=1e00000\0" \
  315. "fdtfile=8544ds/mpc8544ds.dtb\0" \
  316. "bdev=sda3\0"
  317. #define CONFIG_NFSBOOTCOMMAND \
  318. "setenv bootargs root=/dev/nfs rw " \
  319. "nfsroot=$serverip:$rootpath " \
  320. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  321. "console=$consoledev,$baudrate $othbootargs;" \
  322. "tftp $loadaddr $bootfile;" \
  323. "tftp $fdtaddr $fdtfile;" \
  324. "bootm $loadaddr - $fdtaddr"
  325. #define CONFIG_RAMBOOTCOMMAND \
  326. "setenv bootargs root=/dev/ram rw " \
  327. "console=$consoledev,$baudrate $othbootargs;" \
  328. "tftp $ramdiskaddr $ramdiskfile;" \
  329. "tftp $loadaddr $bootfile;" \
  330. "tftp $fdtaddr $fdtfile;" \
  331. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  332. #define CONFIG_BOOTCOMMAND \
  333. "setenv bootargs root=/dev/$bdev rw " \
  334. "console=$consoledev,$baudrate $othbootargs;" \
  335. "tftp $loadaddr $bootfile;" \
  336. "tftp $fdtaddr $fdtfile;" \
  337. "bootm $loadaddr - $fdtaddr"
  338. #endif /* __CONFIG_H */