MPC8536DS.h 20 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc.
  4. */
  5. /*
  6. * mpc8536ds board configuration file
  7. *
  8. */
  9. #ifndef __CONFIG_H
  10. #define __CONFIG_H
  11. #include "../board/freescale/common/ics307_clk.h"
  12. #ifdef CONFIG_SDCARD
  13. #define CONFIG_RAMBOOT_SDCARD 1
  14. #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
  15. #endif
  16. #ifdef CONFIG_SPIFLASH
  17. #define CONFIG_RAMBOOT_SPIFLASH 1
  18. #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
  19. #endif
  20. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  21. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  22. #endif
  23. #ifndef CONFIG_SYS_MONITOR_BASE
  24. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  25. #endif
  26. #define CONFIG_PCI1 1 /* Enable PCI controller 1 */
  27. #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
  28. #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
  29. #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
  30. #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
  31. #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
  32. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  33. #define CONFIG_ENV_OVERWRITE
  34. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
  35. #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
  36. #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
  37. /*
  38. * These can be toggled for performance analysis, otherwise use default.
  39. */
  40. #define CONFIG_L2_CACHE /* toggle L2 cache */
  41. #define CONFIG_BTB /* toggle branch predition */
  42. #define CONFIG_ENABLE_36BIT_PHYS 1
  43. #ifdef CONFIG_PHYS_64BIT
  44. #define CONFIG_ADDR_MAP 1
  45. #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
  46. #endif
  47. #define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */
  48. #define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */
  49. /*
  50. * Config the L2 Cache as L2 SRAM
  51. */
  52. #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
  53. #ifdef CONFIG_PHYS_64BIT
  54. #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
  55. #else
  56. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  57. #endif
  58. #define CONFIG_SYS_L2_SIZE (512 << 10)
  59. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  60. #define CONFIG_SYS_CCSRBAR 0xffe00000
  61. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  62. #if defined(CONFIG_NAND_SPL)
  63. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  64. #endif
  65. /* DDR Setup */
  66. #define CONFIG_VERY_BIG_RAM
  67. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
  68. #define CONFIG_DDR_SPD
  69. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
  70. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  71. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  72. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  73. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  74. #define CONFIG_CHIP_SELECTS_PER_CTRL 2
  75. /* I2C addresses of SPD EEPROMs */
  76. #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
  77. #define CONFIG_SYS_SPD_BUS_NUM 1
  78. /* These are used when DDR doesn't use SPD. */
  79. #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
  80. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
  81. #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
  82. #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  83. #define CONFIG_SYS_DDR_TIMING_0 0x00260802
  84. #define CONFIG_SYS_DDR_TIMING_1 0x3935d322
  85. #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
  86. #define CONFIG_SYS_DDR_MODE_1 0x00480432
  87. #define CONFIG_SYS_DDR_MODE_2 0x00000000
  88. #define CONFIG_SYS_DDR_INTERVAL 0x06180100
  89. #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
  90. #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
  91. #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
  92. #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
  93. #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */
  94. #define CONFIG_SYS_DDR_CONTROL2 0x04400010
  95. #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
  96. #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
  97. #define CONFIG_SYS_DDR_SBE 0x00010000
  98. /* Make sure required options are set */
  99. #ifndef CONFIG_SPD_EEPROM
  100. #error ("CONFIG_SPD_EEPROM is required")
  101. #endif
  102. #undef CONFIG_CLOCKS_IN_MHZ
  103. /*
  104. * Memory map -- xxx -this is wrong, needs updating
  105. *
  106. * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
  107. * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
  108. * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
  109. * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
  110. *
  111. * Localbus cacheable (TBD)
  112. * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
  113. *
  114. * Localbus non-cacheable
  115. * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable
  116. * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
  117. * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
  118. * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
  119. * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
  120. * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
  121. */
  122. /*
  123. * Local Bus Definitions
  124. */
  125. #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
  126. #ifdef CONFIG_PHYS_64BIT
  127. #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
  128. #else
  129. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  130. #endif
  131. #define CONFIG_FLASH_BR_PRELIM \
  132. (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
  133. #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
  134. #define CONFIG_SYS_BR1_PRELIM \
  135. (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
  136. | BR_PS_16 | BR_V)
  137. #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
  138. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \
  139. CONFIG_SYS_FLASH_BASE_PHYS }
  140. #define CONFIG_SYS_FLASH_QUIET_TEST
  141. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  142. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  143. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  144. #undef CONFIG_SYS_FLASH_CHECKSUM
  145. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  146. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  147. #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
  148. #define CONFIG_SYS_RAMBOOT
  149. #else
  150. #undef CONFIG_SYS_RAMBOOT
  151. #endif
  152. #define CONFIG_SYS_FLASH_EMPTY_INFO
  153. #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
  154. #define CONFIG_HWCONFIG /* enable hwconfig */
  155. #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
  156. #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
  157. #ifdef CONFIG_PHYS_64BIT
  158. #define PIXIS_BASE_PHYS 0xfffdf0000ull
  159. #else
  160. #define PIXIS_BASE_PHYS PIXIS_BASE
  161. #endif
  162. #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
  163. #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
  164. #define PIXIS_ID 0x0 /* Board ID at offset 0 */
  165. #define PIXIS_VER 0x1 /* Board version at offset 1 */
  166. #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
  167. #define PIXIS_CSR 0x3 /* PIXIS General control/status register */
  168. #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
  169. #define PIXIS_PWR 0x5 /* PIXIS Power status register */
  170. #define PIXIS_AUX 0x6 /* Auxiliary 1 register */
  171. #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
  172. #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
  173. #define PIXIS_VCTL 0x10 /* VELA Control Register */
  174. #define PIXIS_VSTAT 0x11 /* VELA Status Register */
  175. #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
  176. #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
  177. #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
  178. #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
  179. #define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */
  180. #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
  181. #define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */
  182. #define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */
  183. #define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */
  184. #define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */
  185. #define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */
  186. #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
  187. #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
  188. #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
  189. #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */
  190. #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */
  191. #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */
  192. #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */
  193. #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */
  194. #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */
  195. #define PIXIS_VWATCH 0x24 /* Watchdog Register */
  196. #define PIXIS_LED 0x25 /* LED Register */
  197. #define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */
  198. /* old pixis referenced names */
  199. #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
  200. #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
  201. #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e
  202. #define CONFIG_SYS_INIT_RAM_LOCK 1
  203. #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
  204. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
  205. #define CONFIG_SYS_GBL_DATA_OFFSET \
  206. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  207. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  208. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
  209. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
  210. #ifndef CONFIG_NAND_SPL
  211. #define CONFIG_SYS_NAND_BASE 0xffa00000
  212. #ifdef CONFIG_PHYS_64BIT
  213. #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
  214. #else
  215. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  216. #endif
  217. #else
  218. #define CONFIG_SYS_NAND_BASE 0xfff00000
  219. #ifdef CONFIG_PHYS_64BIT
  220. #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
  221. #else
  222. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  223. #endif
  224. #endif
  225. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
  226. CONFIG_SYS_NAND_BASE + 0x40000, \
  227. CONFIG_SYS_NAND_BASE + 0x80000, \
  228. CONFIG_SYS_NAND_BASE + 0xC0000}
  229. #define CONFIG_SYS_MAX_NAND_DEVICE 4
  230. #define CONFIG_NAND_FSL_ELBC 1
  231. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  232. /* NAND boot: 4K NAND loader config */
  233. #define CONFIG_SYS_NAND_SPL_SIZE 0x1000
  234. #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
  235. #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
  236. #define CONFIG_SYS_NAND_U_BOOT_START \
  237. (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
  238. #define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
  239. #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
  240. #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
  241. /* NAND flash config */
  242. #define CONFIG_SYS_NAND_BR_PRELIM \
  243. (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  244. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  245. | BR_PS_8 /* Port Size = 8 bit */ \
  246. | BR_MS_FCM /* MSEL = FCM */ \
  247. | BR_V) /* valid */
  248. #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
  249. | OR_FCM_PGS /* Large Page*/ \
  250. | OR_FCM_CSCT \
  251. | OR_FCM_CST \
  252. | OR_FCM_CHT \
  253. | OR_FCM_SCY_1 \
  254. | OR_FCM_TRLX \
  255. | OR_FCM_EHTR)
  256. #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
  257. #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
  258. #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
  259. #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  260. #define CONFIG_SYS_BR4_PRELIM \
  261. (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
  262. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  263. | BR_PS_8 /* Port Size = 8 bit */ \
  264. | BR_MS_FCM /* MSEL = FCM */ \
  265. | BR_V) /* valid */
  266. #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  267. #define CONFIG_SYS_BR5_PRELIM \
  268. (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \
  269. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  270. | BR_PS_8 /* Port Size = 8 bit */ \
  271. | BR_MS_FCM /* MSEL = FCM */ \
  272. | BR_V) /* valid */
  273. #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  274. #define CONFIG_SYS_BR6_PRELIM \
  275. (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \
  276. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  277. | BR_PS_8 /* Port Size = 8 bit */ \
  278. | BR_MS_FCM /* MSEL = FCM */ \
  279. | BR_V) /* valid */
  280. #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  281. /* Serial Port - controlled on board with jumper J8
  282. * open - index 2
  283. * shorted - index 1
  284. */
  285. #define CONFIG_SYS_NS16550_SERIAL
  286. #define CONFIG_SYS_NS16550_REG_SIZE 1
  287. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  288. #ifdef CONFIG_NAND_SPL
  289. #define CONFIG_NS16550_MIN_FUNCTIONS
  290. #endif
  291. #define CONFIG_SYS_BAUDRATE_TABLE \
  292. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  293. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
  294. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
  295. /*
  296. * I2C
  297. */
  298. #define CONFIG_SYS_I2C
  299. #define CONFIG_SYS_I2C_FSL
  300. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  301. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  302. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  303. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  304. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  305. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  306. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
  307. /*
  308. * I2C2 EEPROM
  309. */
  310. #define CONFIG_ID_EEPROM
  311. #ifdef CONFIG_ID_EEPROM
  312. #define CONFIG_SYS_I2C_EEPROM_NXID
  313. #endif
  314. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  315. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  316. #define CONFIG_SYS_EEPROM_BUS_NUM 1
  317. /*
  318. * General PCI
  319. * Memory space is mapped 1-1, but I/O space must start from 0.
  320. */
  321. #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
  322. #ifdef CONFIG_PHYS_64BIT
  323. #define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000
  324. #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
  325. #else
  326. #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
  327. #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
  328. #endif
  329. #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
  330. #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000
  331. #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
  332. #ifdef CONFIG_PHYS_64BIT
  333. #define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull
  334. #else
  335. #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000
  336. #endif
  337. #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
  338. /* controller 1, Slot 1, tgtid 1, Base address a000 */
  339. #define CONFIG_SYS_PCIE1_NAME "Slot 1"
  340. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
  341. #ifdef CONFIG_PHYS_64BIT
  342. #define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000
  343. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull
  344. #else
  345. #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
  346. #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
  347. #endif
  348. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */
  349. #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000
  350. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  351. #ifdef CONFIG_PHYS_64BIT
  352. #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull
  353. #else
  354. #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000
  355. #endif
  356. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  357. /* controller 2, Slot 2, tgtid 2, Base address 9000 */
  358. #define CONFIG_SYS_PCIE2_NAME "Slot 2"
  359. #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000
  360. #ifdef CONFIG_PHYS_64BIT
  361. #define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000
  362. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull
  363. #else
  364. #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000
  365. #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000
  366. #endif
  367. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */
  368. #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
  369. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  370. #ifdef CONFIG_PHYS_64BIT
  371. #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull
  372. #else
  373. #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
  374. #endif
  375. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  376. /* controller 3, direct to uli, tgtid 3, Base address 8000 */
  377. #define CONFIG_SYS_PCIE3_NAME "Slot 3"
  378. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
  379. #ifdef CONFIG_PHYS_64BIT
  380. #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  381. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
  382. #else
  383. #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
  384. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
  385. #endif
  386. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
  387. #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000
  388. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  389. #ifdef CONFIG_PHYS_64BIT
  390. #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull
  391. #else
  392. #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000
  393. #endif
  394. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  395. #if defined(CONFIG_PCI)
  396. /*PCIE video card used*/
  397. #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT
  398. /*PCI video card used*/
  399. /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
  400. /* video */
  401. #if defined(CONFIG_VIDEO)
  402. #define CONFIG_BIOSEMU
  403. #define CONFIG_ATI_RADEON_FB
  404. #define CONFIG_VIDEO_LOGO
  405. #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT
  406. #endif
  407. #undef CONFIG_EEPRO100
  408. #undef CONFIG_TULIP
  409. #ifndef CONFIG_PCI_PNP
  410. #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
  411. #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
  412. #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
  413. #endif
  414. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  415. #endif /* CONFIG_PCI */
  416. /* SATA */
  417. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  418. #define CONFIG_SATA1
  419. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  420. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  421. #define CONFIG_SATA2
  422. #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  423. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  424. #ifdef CONFIG_FSL_SATA
  425. #define CONFIG_LBA48
  426. #endif
  427. #if defined(CONFIG_TSEC_ENET)
  428. #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
  429. #define CONFIG_TSEC1 1
  430. #define CONFIG_TSEC1_NAME "eTSEC1"
  431. #define CONFIG_TSEC3 1
  432. #define CONFIG_TSEC3_NAME "eTSEC3"
  433. #define CONFIG_FSL_SGMII_RISER 1
  434. #define SGMII_RISER_PHY_OFFSET 0x1c
  435. #define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */
  436. #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */
  437. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  438. #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  439. #define TSEC1_PHYIDX 0
  440. #define TSEC3_PHYIDX 0
  441. #define CONFIG_ETHPRIME "eTSEC1"
  442. #endif /* CONFIG_TSEC_ENET */
  443. /*
  444. * Environment
  445. */
  446. #if defined(CONFIG_SYS_RAMBOOT)
  447. #if defined(CONFIG_RAMBOOT_SPIFLASH)
  448. #elif defined(CONFIG_RAMBOOT_SDCARD)
  449. #define CONFIG_FSL_FIXED_MMC_LOCATION
  450. #define CONFIG_SYS_MMC_ENV_DEV 0
  451. #endif
  452. #endif
  453. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  454. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  455. #undef CONFIG_WATCHDOG /* watchdog disabled */
  456. #ifdef CONFIG_MMC
  457. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  458. #endif
  459. /*
  460. * USB
  461. */
  462. #define CONFIG_HAS_FSL_MPH_USB
  463. #ifdef CONFIG_HAS_FSL_MPH_USB
  464. #ifdef CONFIG_USB_EHCI_HCD
  465. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  466. #define CONFIG_USB_EHCI_FSL
  467. #endif
  468. #endif
  469. /*
  470. * Miscellaneous configurable options
  471. */
  472. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  473. /*
  474. * For booting Linux, the board info and command line data
  475. * have to be in the first 64 MB of memory, since this is
  476. * the maximum mapped by the Linux kernel during initialization.
  477. */
  478. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
  479. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  480. #if defined(CONFIG_CMD_KGDB)
  481. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  482. #endif
  483. /*
  484. * Environment Configuration
  485. */
  486. /* The mac addresses for all ethernet interface */
  487. #if defined(CONFIG_TSEC_ENET)
  488. #define CONFIG_HAS_ETH0
  489. #define CONFIG_HAS_ETH1
  490. #define CONFIG_HAS_ETH2
  491. #define CONFIG_HAS_ETH3
  492. #endif
  493. #define CONFIG_IPADDR 192.168.1.254
  494. #define CONFIG_HOSTNAME "unknown"
  495. #define CONFIG_ROOTPATH "/opt/nfsroot"
  496. #define CONFIG_BOOTFILE "uImage"
  497. #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
  498. #define CONFIG_SERVERIP 192.168.1.1
  499. #define CONFIG_GATEWAYIP 192.168.1.1
  500. #define CONFIG_NETMASK 255.255.255.0
  501. /* default location for tftp and bootm */
  502. #define CONFIG_LOADADDR 1000000
  503. #define CONFIG_EXTRA_ENV_SETTINGS \
  504. "netdev=eth0\0" \
  505. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  506. "tftpflash=tftpboot $loadaddr $uboot; " \
  507. "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
  508. " +$filesize; " \
  509. "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
  510. " +$filesize; " \
  511. "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  512. " $filesize; " \
  513. "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
  514. " +$filesize; " \
  515. "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  516. " $filesize\0" \
  517. "consoledev=ttyS0\0" \
  518. "ramdiskaddr=2000000\0" \
  519. "ramdiskfile=8536ds/ramdisk.uboot\0" \
  520. "fdtaddr=1e00000\0" \
  521. "fdtfile=8536ds/mpc8536ds.dtb\0" \
  522. "bdev=sda3\0" \
  523. "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
  524. #define CONFIG_HDBOOT \
  525. "setenv bootargs root=/dev/$bdev rw " \
  526. "console=$consoledev,$baudrate $othbootargs;" \
  527. "tftp $loadaddr $bootfile;" \
  528. "tftp $fdtaddr $fdtfile;" \
  529. "bootm $loadaddr - $fdtaddr"
  530. #define CONFIG_NFSBOOTCOMMAND \
  531. "setenv bootargs root=/dev/nfs rw " \
  532. "nfsroot=$serverip:$rootpath " \
  533. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  534. "console=$consoledev,$baudrate $othbootargs;" \
  535. "tftp $loadaddr $bootfile;" \
  536. "tftp $fdtaddr $fdtfile;" \
  537. "bootm $loadaddr - $fdtaddr"
  538. #define CONFIG_RAMBOOTCOMMAND \
  539. "setenv bootargs root=/dev/ram rw " \
  540. "console=$consoledev,$baudrate $othbootargs;" \
  541. "tftp $ramdiskaddr $ramdiskfile;" \
  542. "tftp $loadaddr $bootfile;" \
  543. "tftp $fdtaddr $fdtfile;" \
  544. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  545. #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
  546. #endif /* __CONFIG_H */