MPC837XERDB.h 12 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2007 Freescale Semiconductor, Inc.
  4. * Kevin Lam <kevin.lam@freescale.com>
  5. * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
  6. */
  7. #ifndef __CONFIG_H
  8. #define __CONFIG_H
  9. /*
  10. * High Level Configuration Options
  11. */
  12. #define CONFIG_E300 1 /* E300 family */
  13. #define CONFIG_HWCONFIG
  14. /*
  15. * On-board devices
  16. */
  17. #define CONFIG_VSC7385_ENET
  18. /* System performance - define the value i.e. CONFIG_SYS_XXX
  19. */
  20. /* System Clock Configuration Register */
  21. #define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */
  22. #define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */
  23. #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */
  24. /*
  25. * System IO Config
  26. */
  27. #define CONFIG_SYS_SICRH 0x08200000
  28. #define CONFIG_SYS_SICRL 0x00000000
  29. /*
  30. * Output Buffer Impedance
  31. */
  32. #define CONFIG_SYS_OBIR 0x30100000
  33. /*
  34. * Device configurations
  35. */
  36. /* Vitesse 7385 */
  37. #ifdef CONFIG_VSC7385_ENET
  38. #define CONFIG_TSEC2
  39. /* The flash address and size of the VSC7385 firmware image */
  40. #define CONFIG_VSC7385_IMAGE 0xFE7FE000
  41. #define CONFIG_VSC7385_IMAGE_SIZE 8192
  42. #endif
  43. /*
  44. * DDR Setup
  45. */
  46. #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
  47. #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000
  48. #define CONFIG_SYS_83XX_DDR_USES_CS0
  49. #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
  50. #undef CONFIG_DDR_ECC /* support DDR ECC function */
  51. #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
  52. #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
  53. /*
  54. * Manually set up DDR parameters
  55. */
  56. #define CONFIG_SYS_DDR_SIZE 256 /* MB */
  57. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
  58. #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
  59. | CSCONFIG_ODT_WR_ONLY_CURRENT \
  60. | CSCONFIG_ROW_BIT_13 \
  61. | CSCONFIG_COL_BIT_10)
  62. #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  63. #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  64. | (0 << TIMING_CFG0_WRT_SHIFT) \
  65. | (0 << TIMING_CFG0_RRT_SHIFT) \
  66. | (0 << TIMING_CFG0_WWT_SHIFT) \
  67. | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  68. | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  69. | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  70. | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  71. /* 0x00260802 */ /* DDR400 */
  72. #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
  73. | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  74. | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
  75. | (7 << TIMING_CFG1_CASLAT_SHIFT) \
  76. | (13 << TIMING_CFG1_REFREC_SHIFT) \
  77. | (3 << TIMING_CFG1_WRREC_SHIFT) \
  78. | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  79. | (2 << TIMING_CFG1_WRTORD_SHIFT))
  80. /* 0x3937d322 */
  81. #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
  82. | (5 << TIMING_CFG2_CPO_SHIFT) \
  83. | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  84. | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  85. | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  86. | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  87. | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
  88. /* 0x02984cc8 */
  89. #define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
  90. | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  91. /* 0x06090100 */
  92. #if defined(CONFIG_DDR_2T_TIMING)
  93. #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
  94. | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  95. | SDRAM_CFG_32_BE \
  96. | SDRAM_CFG_2T_EN)
  97. /* 0x43088000 */
  98. #else
  99. #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
  100. | SDRAM_CFG_SDRAM_TYPE_DDR2)
  101. /* 0x43000000 */
  102. #endif
  103. #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
  104. #define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
  105. | (0x0442 << SDRAM_MODE_SD_SHIFT))
  106. /* 0x04400442 */ /* DDR400 */
  107. #define CONFIG_SYS_DDR_MODE2 0x00000000
  108. /*
  109. * Memory test
  110. */
  111. #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
  112. #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
  113. #define CONFIG_SYS_MEMTEST_END 0x0ef70010
  114. /*
  115. * The reserved memory
  116. */
  117. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  118. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  119. #define CONFIG_SYS_RAMBOOT
  120. #else
  121. #undef CONFIG_SYS_RAMBOOT
  122. #endif
  123. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
  124. #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
  125. /*
  126. * Initial RAM Base Address Setup
  127. */
  128. #define CONFIG_SYS_INIT_RAM_LOCK 1
  129. #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
  130. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
  131. #define CONFIG_SYS_GBL_DATA_OFFSET \
  132. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  133. #define CONFIG_FSL_ELBC 1
  134. /*
  135. * FLASH on the Local Bus
  136. */
  137. #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
  138. #define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */
  139. #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
  140. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  141. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
  142. #undef CONFIG_SYS_FLASH_CHECKSUM
  143. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  144. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  145. /*
  146. * NAND Flash on the Local Bus
  147. */
  148. #define CONFIG_SYS_NAND_BASE 0xE0600000
  149. /* Vitesse 7385 */
  150. #define CONFIG_SYS_VSC7385_BASE 0xF0000000
  151. /*
  152. * Serial Port
  153. */
  154. #define CONFIG_SYS_NS16550_SERIAL
  155. #define CONFIG_SYS_NS16550_REG_SIZE 1
  156. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  157. #define CONFIG_SYS_BAUDRATE_TABLE \
  158. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  159. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
  160. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
  161. /* SERDES */
  162. #define CONFIG_FSL_SERDES
  163. #define CONFIG_FSL_SERDES1 0xe3000
  164. #define CONFIG_FSL_SERDES2 0xe3100
  165. /* I2C */
  166. #define CONFIG_SYS_I2C
  167. #define CONFIG_SYS_I2C_FSL
  168. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  169. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  170. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  171. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
  172. /*
  173. * Config on-board RTC
  174. */
  175. #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
  176. #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
  177. /*
  178. * General PCI
  179. * Addresses are mapped 1-1.
  180. */
  181. #define CONFIG_SYS_PCI_MEM_BASE 0x80000000
  182. #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
  183. #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
  184. #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
  185. #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
  186. #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
  187. #define CONFIG_SYS_PCI_IO_BASE 0x00000000
  188. #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
  189. #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
  190. #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
  191. #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
  192. #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
  193. #define CONFIG_SYS_PCIE1_BASE 0xA0000000
  194. #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
  195. #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
  196. #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
  197. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
  198. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
  199. #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
  200. #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
  201. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
  202. #define CONFIG_SYS_PCIE2_BASE 0xC0000000
  203. #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
  204. #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
  205. #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
  206. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
  207. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
  208. #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
  209. #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
  210. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
  211. #ifdef CONFIG_PCI
  212. #define CONFIG_PCI_INDIRECT_BRIDGE
  213. #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  214. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
  215. #endif /* CONFIG_PCI */
  216. /*
  217. * TSEC
  218. */
  219. #ifdef CONFIG_TSEC_ENET
  220. #define CONFIG_GMII /* MII PHY management */
  221. #define CONFIG_TSEC1
  222. #ifdef CONFIG_TSEC1
  223. #define CONFIG_HAS_ETH0
  224. #define CONFIG_TSEC1_NAME "TSEC0"
  225. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  226. #define TSEC1_PHY_ADDR 2
  227. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  228. #define TSEC1_PHYIDX 0
  229. #endif
  230. #ifdef CONFIG_TSEC2
  231. #define CONFIG_HAS_ETH1
  232. #define CONFIG_TSEC2_NAME "TSEC1"
  233. #define CONFIG_SYS_TSEC2_OFFSET 0x25000
  234. #define TSEC2_PHY_ADDR 0x1c
  235. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  236. #define TSEC2_PHYIDX 0
  237. #endif
  238. /* Options are: TSEC[0-1] */
  239. #define CONFIG_ETHPRIME "TSEC0"
  240. #endif
  241. /*
  242. * SATA
  243. */
  244. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  245. #define CONFIG_SATA1
  246. #define CONFIG_SYS_SATA1_OFFSET 0x18000
  247. #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
  248. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  249. #define CONFIG_SATA2
  250. #define CONFIG_SYS_SATA2_OFFSET 0x19000
  251. #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
  252. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  253. #ifdef CONFIG_FSL_SATA
  254. #define CONFIG_LBA48
  255. #endif
  256. /*
  257. * Environment
  258. */
  259. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  260. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  261. /*
  262. * BOOTP options
  263. */
  264. #define CONFIG_BOOTP_BOOTFILESIZE
  265. /*
  266. * Command line configuration.
  267. */
  268. #undef CONFIG_WATCHDOG /* watchdog disabled */
  269. #ifdef CONFIG_MMC
  270. #define CONFIG_FSL_ESDHC_PIN_MUX
  271. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
  272. #endif
  273. /*
  274. * Miscellaneous configurable options
  275. */
  276. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  277. /*
  278. * For booting Linux, the board info and command line data
  279. * have to be in the first 256 MB of memory, since this is
  280. * the maximum mapped by the Linux kernel during initialization.
  281. */
  282. #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
  283. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  284. #if defined(CONFIG_CMD_KGDB)
  285. #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
  286. #endif
  287. /*
  288. * Environment Configuration
  289. */
  290. #define CONFIG_ENV_OVERWRITE
  291. #define CONFIG_HAS_FSL_DR_USB
  292. #define CONFIG_USB_EHCI_FSL
  293. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  294. #define CONFIG_NETDEV "eth1"
  295. #define CONFIG_HOSTNAME "mpc837x_rdb"
  296. #define CONFIG_ROOTPATH "/nfsroot"
  297. #define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot"
  298. #define CONFIG_BOOTFILE "uImage"
  299. /* U-Boot image on TFTP server */
  300. #define CONFIG_UBOOTPATH "u-boot.bin"
  301. #define CONFIG_FDTFILE "mpc8379_rdb.dtb"
  302. /* default location for tftp and bootm */
  303. #define CONFIG_LOADADDR 800000
  304. #define CONFIG_EXTRA_ENV_SETTINGS \
  305. "netdev=" CONFIG_NETDEV "\0" \
  306. "uboot=" CONFIG_UBOOTPATH "\0" \
  307. "tftpflash=tftp $loadaddr $uboot;" \
  308. "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
  309. " +$filesize; " \
  310. "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
  311. " +$filesize; " \
  312. "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  313. " $filesize; " \
  314. "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
  315. " +$filesize; " \
  316. "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  317. " $filesize\0" \
  318. "fdtaddr=780000\0" \
  319. "fdtfile=" CONFIG_FDTFILE "\0" \
  320. "ramdiskaddr=1000000\0" \
  321. "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \
  322. "console=ttyS0\0" \
  323. "setbootargs=setenv bootargs " \
  324. "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
  325. "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
  326. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
  327. "$netdev:off " \
  328. "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
  329. #define CONFIG_NFSBOOTCOMMAND \
  330. "setenv rootdev /dev/nfs;" \
  331. "run setbootargs;" \
  332. "run setipargs;" \
  333. "tftp $loadaddr $bootfile;" \
  334. "tftp $fdtaddr $fdtfile;" \
  335. "bootm $loadaddr - $fdtaddr"
  336. #define CONFIG_RAMBOOTCOMMAND \
  337. "setenv rootdev /dev/ram;" \
  338. "run setbootargs;" \
  339. "tftp $ramdiskaddr $ramdiskfile;" \
  340. "tftp $loadaddr $bootfile;" \
  341. "tftp $fdtaddr $fdtfile;" \
  342. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  343. #endif /* __CONFIG_H */