MPC837XEMDS.h 11 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2007 Freescale Semiconductor, Inc.
  4. * Dave Liu <daveliu@freescale.com>
  5. */
  6. #ifndef __CONFIG_H
  7. #define __CONFIG_H
  8. /*
  9. * High Level Configuration Options
  10. */
  11. #define CONFIG_E300 1 /* E300 family */
  12. /*
  13. * IP blocks clock configuration
  14. */
  15. #define CONFIG_SYS_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */
  16. #define CONFIG_SYS_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */
  17. #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */
  18. /*
  19. * System IO Config
  20. */
  21. #define CONFIG_SYS_SICRH 0x00000000
  22. #define CONFIG_SYS_SICRL 0x00000000
  23. /*
  24. * Output Buffer Impedance
  25. */
  26. #define CONFIG_SYS_OBIR 0x31100000
  27. #define CONFIG_HWCONFIG
  28. /*
  29. * DDR Setup
  30. */
  31. #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
  32. #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  33. #define CONFIG_SYS_83XX_DDR_USES_CS0
  34. #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \
  35. | DDRCDR_ODT \
  36. | DDRCDR_Q_DRN)
  37. /* 0x80080001 */ /* ODT 150ohm on SoC */
  38. #undef CONFIG_DDR_ECC /* support DDR ECC function */
  39. #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
  40. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
  41. #define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
  42. #if defined(CONFIG_SPD_EEPROM)
  43. #define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */
  44. #else
  45. /*
  46. * Manually set up DDR parameters
  47. * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM
  48. * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5
  49. */
  50. #define CONFIG_SYS_DDR_SIZE 512 /* MB */
  51. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
  52. #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
  53. | CSCONFIG_ODT_RD_NEVER /* ODT_RD to none */ \
  54. | CSCONFIG_ODT_WR_ONLY_CURRENT /* ODT_WR to CSn */ \
  55. | CSCONFIG_ROW_BIT_14 \
  56. | CSCONFIG_COL_BIT_10)
  57. /* 0x80010202 */
  58. #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  59. #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  60. | (0 << TIMING_CFG0_WRT_SHIFT) \
  61. | (0 << TIMING_CFG0_RRT_SHIFT) \
  62. | (0 << TIMING_CFG0_WWT_SHIFT) \
  63. | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  64. | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  65. | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  66. | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  67. /* 0x00620802 */
  68. #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
  69. | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  70. | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
  71. | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  72. | (13 << TIMING_CFG1_REFREC_SHIFT) \
  73. | (3 << TIMING_CFG1_WRREC_SHIFT) \
  74. | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  75. | (2 << TIMING_CFG1_WRTORD_SHIFT))
  76. /* 0x3935d322 */
  77. #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
  78. | (6 << TIMING_CFG2_CPO_SHIFT) \
  79. | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  80. | (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  81. | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  82. | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  83. | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
  84. /* 0x131088c8 */
  85. #define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \
  86. | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  87. /* 0x03E00100 */
  88. #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
  89. #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
  90. #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
  91. | (0x1432 << SDRAM_MODE_SD_SHIFT))
  92. /* ODT 150ohm CL=3, AL=1 on SDRAM */
  93. #define CONFIG_SYS_DDR_MODE2 0x00000000
  94. #endif
  95. /*
  96. * Memory test
  97. */
  98. #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
  99. #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
  100. #define CONFIG_SYS_MEMTEST_END 0x00140000
  101. /*
  102. * The reserved memory
  103. */
  104. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  105. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  106. #define CONFIG_SYS_RAMBOOT
  107. #else
  108. #undef CONFIG_SYS_RAMBOOT
  109. #endif
  110. /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
  111. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
  112. #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
  113. /*
  114. * Initial RAM Base Address Setup
  115. */
  116. #define CONFIG_SYS_INIT_RAM_LOCK 1
  117. #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
  118. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
  119. #define CONFIG_SYS_GBL_DATA_OFFSET \
  120. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  121. #define CONFIG_FSL_ELBC 1
  122. /*
  123. * FLASH on the Local Bus
  124. */
  125. #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
  126. #define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */
  127. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  128. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
  129. #undef CONFIG_SYS_FLASH_CHECKSUM
  130. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  131. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  132. /*
  133. * BCSR on the Local Bus
  134. */
  135. #define CONFIG_SYS_BCSR 0xF8000000
  136. /* Access window base at BCSR base */
  137. /*
  138. * NAND Flash on the Local Bus
  139. */
  140. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  141. #define CONFIG_NAND_FSL_ELBC 1
  142. #define CONFIG_SYS_NAND_BASE 0xE0600000
  143. /*
  144. * Serial Port
  145. */
  146. #define CONFIG_SYS_NS16550_SERIAL
  147. #define CONFIG_SYS_NS16550_REG_SIZE 1
  148. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  149. #define CONFIG_SYS_BAUDRATE_TABLE \
  150. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  151. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
  152. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
  153. /* I2C */
  154. #define CONFIG_SYS_I2C
  155. #define CONFIG_SYS_I2C_FSL
  156. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  157. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  158. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  159. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
  160. /*
  161. * Config on-board RTC
  162. */
  163. #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
  164. #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
  165. /*
  166. * General PCI
  167. * Addresses are mapped 1-1.
  168. */
  169. #define CONFIG_SYS_PCI_MEM_BASE 0x80000000
  170. #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
  171. #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
  172. #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
  173. #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
  174. #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
  175. #define CONFIG_SYS_PCI_IO_BASE 0x00000000
  176. #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
  177. #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
  178. #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
  179. #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
  180. #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
  181. #define CONFIG_SYS_PCIE1_BASE 0xA0000000
  182. #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
  183. #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
  184. #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
  185. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
  186. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
  187. #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
  188. #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
  189. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
  190. #define CONFIG_SYS_PCIE2_BASE 0xC0000000
  191. #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
  192. #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
  193. #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
  194. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
  195. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
  196. #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
  197. #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
  198. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
  199. #ifdef CONFIG_PCI
  200. #define CONFIG_PCI_INDIRECT_BRIDGE
  201. #ifndef __ASSEMBLY__
  202. extern int board_pci_host_broken(void);
  203. #endif
  204. #define CONFIG_PCIE
  205. #define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */
  206. #define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */
  207. #define CONFIG_USB_EHCI_FSL
  208. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  209. #undef CONFIG_EEPRO100
  210. #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  211. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
  212. #endif /* CONFIG_PCI */
  213. /*
  214. * TSEC
  215. */
  216. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  217. #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
  218. #define CONFIG_SYS_TSEC2_OFFSET 0x25000
  219. #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
  220. /*
  221. * TSEC ethernet configuration
  222. */
  223. #define CONFIG_TSEC1 1
  224. #define CONFIG_TSEC1_NAME "eTSEC0"
  225. #define CONFIG_TSEC2 1
  226. #define CONFIG_TSEC2_NAME "eTSEC1"
  227. #define TSEC1_PHY_ADDR 2
  228. #define TSEC2_PHY_ADDR 3
  229. #define TSEC1_PHY_ADDR_SGMII 8
  230. #define TSEC2_PHY_ADDR_SGMII 4
  231. #define TSEC1_PHYIDX 0
  232. #define TSEC2_PHYIDX 0
  233. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  234. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  235. /* Options are: TSEC[0-1] */
  236. #define CONFIG_ETHPRIME "eTSEC1"
  237. /* SERDES */
  238. #define CONFIG_FSL_SERDES
  239. #define CONFIG_FSL_SERDES1 0xe3000
  240. #define CONFIG_FSL_SERDES2 0xe3100
  241. /*
  242. * SATA
  243. */
  244. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  245. #define CONFIG_SATA1
  246. #define CONFIG_SYS_SATA1_OFFSET 0x18000
  247. #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
  248. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  249. #define CONFIG_SATA2
  250. #define CONFIG_SYS_SATA2_OFFSET 0x19000
  251. #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
  252. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  253. #ifdef CONFIG_FSL_SATA
  254. #define CONFIG_LBA48
  255. #endif
  256. /*
  257. * Environment
  258. */
  259. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  260. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  261. /*
  262. * BOOTP options
  263. */
  264. #define CONFIG_BOOTP_BOOTFILESIZE
  265. /*
  266. * Command line configuration.
  267. */
  268. #undef CONFIG_WATCHDOG /* watchdog disabled */
  269. #ifdef CONFIG_MMC
  270. #define CONFIG_FSL_ESDHC_PIN_MUX
  271. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
  272. #endif
  273. /*
  274. * Miscellaneous configurable options
  275. */
  276. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  277. /*
  278. * For booting Linux, the board info and command line data
  279. * have to be in the first 256 MB of memory, since this is
  280. * the maximum mapped by the Linux kernel during initialization.
  281. */
  282. #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
  283. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  284. #if defined(CONFIG_CMD_KGDB)
  285. #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
  286. #endif
  287. /*
  288. * Environment Configuration
  289. */
  290. #define CONFIG_ENV_OVERWRITE
  291. #if defined(CONFIG_TSEC_ENET)
  292. #define CONFIG_HAS_ETH0
  293. #define CONFIG_HAS_ETH1
  294. #endif
  295. #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
  296. #define CONFIG_EXTRA_ENV_SETTINGS \
  297. "netdev=eth0\0" \
  298. "consoledev=ttyS0\0" \
  299. "ramdiskaddr=1000000\0" \
  300. "ramdiskfile=ramfs.83xx\0" \
  301. "fdtaddr=780000\0" \
  302. "fdtfile=mpc8379_mds.dtb\0" \
  303. ""
  304. #define CONFIG_NFSBOOTCOMMAND \
  305. "setenv bootargs root=/dev/nfs rw " \
  306. "nfsroot=$serverip:$rootpath " \
  307. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
  308. "$netdev:off " \
  309. "console=$consoledev,$baudrate $othbootargs;" \
  310. "tftp $loadaddr $bootfile;" \
  311. "tftp $fdtaddr $fdtfile;" \
  312. "bootm $loadaddr - $fdtaddr"
  313. #define CONFIG_RAMBOOTCOMMAND \
  314. "setenv bootargs root=/dev/ram rw " \
  315. "console=$consoledev,$baudrate $othbootargs;" \
  316. "tftp $ramdiskaddr $ramdiskfile;" \
  317. "tftp $loadaddr $bootfile;" \
  318. "tftp $fdtaddr $fdtfile;" \
  319. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  320. #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
  321. #endif /* __CONFIG_H */