MPC8349ITX.h 12 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) Freescale Semiconductor, Inc. 2006.
  4. */
  5. /*
  6. MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
  7. Memory map:
  8. 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
  9. 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
  10. 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
  11. 0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
  12. 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
  13. 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
  14. 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
  15. 0xF001_0000-0xF001_FFFF Local bus expansion slot
  16. 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
  17. 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
  18. 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
  19. I2C address list:
  20. Align. Board
  21. Bus Addr Part No. Description Length Location
  22. ----------------------------------------------------------------
  23. I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64
  24. I2C1 0x20 PCF8574 I2C Expander 0 U8
  25. I2C1 0x21 PCF8574 I2C Expander 0 U10
  26. I2C1 0x38 PCF8574A I2C Expander 0 U8
  27. I2C1 0x39 PCF8574A I2C Expander 0 U10
  28. I2C1 0x51 (DDR) DDR EEPROM 1 U1
  29. I2C1 0x68 DS1339 RTC 1 U68
  30. Note that a given board has *either* a pair of 8574s or a pair of 8574As.
  31. */
  32. #ifndef __CONFIG_H
  33. #define __CONFIG_H
  34. #define CONFIG_MISC_INIT_F
  35. /*
  36. * On-board devices
  37. */
  38. #ifdef CONFIG_TARGET_MPC8349ITX
  39. /* The CF card interface on the back of the board */
  40. #define CONFIG_COMPACT_FLASH
  41. #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */
  42. #define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */
  43. #endif
  44. #define CONFIG_RTC_DS1337
  45. #define CONFIG_SYS_I2C
  46. /*
  47. * Device configurations
  48. */
  49. /* I2C */
  50. #ifdef CONFIG_SYS_I2C
  51. #define CONFIG_SYS_I2C_FSL
  52. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  53. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  54. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  55. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  56. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  57. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  58. #define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */
  59. #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */
  60. #define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */
  61. #define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */
  62. #define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */
  63. #define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */
  64. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */
  65. #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/
  66. #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */
  67. /* Don't probe these addresses: */
  68. #define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \
  69. {1, CONFIG_SYS_I2C_8574_ADDR2}, \
  70. {1, CONFIG_SYS_I2C_8574A_ADDR1}, \
  71. {1, CONFIG_SYS_I2C_8574A_ADDR2} }
  72. /* Bit definitions for the 8574[A] I2C expander */
  73. /* Board revision, 00=0.0, 01=0.1, 10=1.0 */
  74. #define I2C_8574_REVISION 0x03
  75. #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */
  76. #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */
  77. #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */
  78. #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/
  79. #endif
  80. /* Compact Flash */
  81. #ifdef CONFIG_COMPACT_FLASH
  82. #define CONFIG_SYS_IDE_MAXBUS 1
  83. #define CONFIG_SYS_IDE_MAXDEVICE 1
  84. #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
  85. #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE
  86. #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000
  87. #define CONFIG_SYS_ATA_REG_OFFSET 0
  88. #define CONFIG_SYS_ATA_ALT_OFFSET 0x0200
  89. #define CONFIG_SYS_ATA_STRIDE 2
  90. /* If a CF card is not inserted, time out quickly */
  91. #define ATA_RESET_TIME 1
  92. #endif
  93. /*
  94. * SATA
  95. */
  96. #ifdef CONFIG_SATA_SIL3114
  97. #define CONFIG_SYS_SATA_MAX_DEVICE 4
  98. #define CONFIG_LBA48
  99. #endif
  100. #ifdef CONFIG_SYS_USB_HOST
  101. /*
  102. * Support USB
  103. */
  104. #define CONFIG_USB_EHCI_FSL
  105. /* Current USB implementation supports the only USB controller,
  106. * so we have to choose between the MPH or the DR ones */
  107. #if 1
  108. #define CONFIG_HAS_FSL_MPH_USB
  109. #else
  110. #define CONFIG_HAS_FSL_DR_USB
  111. #endif
  112. #endif
  113. /*
  114. * DDR Setup
  115. */
  116. #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
  117. #define CONFIG_SYS_83XX_DDR_USES_CS0
  118. #define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */
  119. #define CONFIG_SYS_MEMTEST_END 0x2000
  120. #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
  121. | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
  122. #define CONFIG_VERY_BIG_RAM
  123. #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20)
  124. #ifdef CONFIG_SYS_I2C
  125. #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
  126. #endif
  127. /* No SPD? Then manually set up DDR parameters */
  128. #ifndef CONFIG_SPD_EEPROM
  129. #define CONFIG_SYS_DDR_SIZE 256 /* Mb */
  130. #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
  131. | CSCONFIG_ROW_BIT_13 \
  132. | CSCONFIG_COL_BIT_10)
  133. #define CONFIG_SYS_DDR_TIMING_1 0x26242321
  134. #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */
  135. #endif
  136. /*
  137. *Flash on the Local Bus
  138. */
  139. #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
  140. #define CONFIG_SYS_FLASH_EMPTY_INFO
  141. /* 127 64KB sectors + 8 8KB sectors per device */
  142. #define CONFIG_SYS_MAX_FLASH_SECT 135
  143. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  144. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  145. #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  146. /* The ITX has two flash chips, but the ITX-GP has only one. To support both
  147. boards, we say we have two, but don't display a message if we find only one. */
  148. #define CONFIG_SYS_FLASH_QUIET_TEST
  149. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  150. #define CONFIG_SYS_FLASH_BANKS_LIST \
  151. {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
  152. #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */
  153. /* Vitesse 7385 */
  154. #ifdef CONFIG_VSC7385_ENET
  155. #define CONFIG_TSEC2
  156. /* The flash address and size of the VSC7385 firmware image */
  157. #define CONFIG_VSC7385_IMAGE 0xFEFFE000
  158. #define CONFIG_VSC7385_IMAGE_SIZE 8192
  159. #endif
  160. /*
  161. * BRx, ORx, LBLAWBARx, and LBLAWARx
  162. */
  163. /* Vitesse 7385 */
  164. #define CONFIG_SYS_VSC7385_BASE 0xF8000000
  165. #define CONFIG_SYS_LED_BASE 0xF9000000
  166. /* Compact Flash */
  167. #ifdef CONFIG_COMPACT_FLASH
  168. #define CONFIG_SYS_CF_BASE 0xF0000000
  169. #endif
  170. /*
  171. * U-Boot memory configuration
  172. */
  173. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  174. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  175. #define CONFIG_SYS_RAMBOOT
  176. #else
  177. #undef CONFIG_SYS_RAMBOOT
  178. #endif
  179. #define CONFIG_SYS_INIT_RAM_LOCK
  180. #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
  181. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
  182. #define CONFIG_SYS_GBL_DATA_OFFSET \
  183. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  184. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  185. /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
  186. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
  187. #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
  188. /*
  189. * Serial Port
  190. */
  191. #define CONFIG_SYS_NS16550_SERIAL
  192. #define CONFIG_SYS_NS16550_REG_SIZE 1
  193. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  194. #define CONFIG_SYS_BAUDRATE_TABLE \
  195. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  196. #define CONSOLE ttyS0
  197. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
  198. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
  199. /*
  200. * PCI
  201. */
  202. #ifdef CONFIG_PCI
  203. #define CONFIG_PCI_INDIRECT_BRIDGE
  204. #define CONFIG_MPC83XX_PCI2
  205. /*
  206. * General PCI
  207. * Addresses are mapped 1-1.
  208. */
  209. #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
  210. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  211. #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
  212. #define CONFIG_SYS_PCI1_MMIO_BASE \
  213. (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
  214. #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
  215. #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
  216. #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
  217. #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
  218. #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
  219. #ifdef CONFIG_MPC83XX_PCI2
  220. #define CONFIG_SYS_PCI2_MEM_BASE \
  221. (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
  222. #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
  223. #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
  224. #define CONFIG_SYS_PCI2_MMIO_BASE \
  225. (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
  226. #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
  227. #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
  228. #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
  229. #define CONFIG_SYS_PCI2_IO_PHYS \
  230. (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
  231. #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */
  232. #endif
  233. #ifndef CONFIG_PCI_PNP
  234. #define PCI_ENET0_IOADDR 0x00000000
  235. #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE
  236. #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */
  237. #endif
  238. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  239. #endif
  240. /* TSEC */
  241. #ifdef CONFIG_TSEC_ENET
  242. #define CONFIG_TSEC1
  243. #ifdef CONFIG_TSEC1
  244. #define CONFIG_HAS_ETH0
  245. #define CONFIG_TSEC1_NAME "TSEC0"
  246. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  247. #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */
  248. #define TSEC1_PHYIDX 0
  249. #define TSEC1_FLAGS TSEC_GIGABIT
  250. #endif
  251. #ifdef CONFIG_TSEC2
  252. #define CONFIG_HAS_ETH1
  253. #define CONFIG_TSEC2_NAME "TSEC1"
  254. #define CONFIG_SYS_TSEC2_OFFSET 0x25000
  255. #define TSEC2_PHY_ADDR 4
  256. #define TSEC2_PHYIDX 0
  257. #define TSEC2_FLAGS TSEC_GIGABIT
  258. #endif
  259. #define CONFIG_ETHPRIME "Freescale TSEC"
  260. #endif
  261. /*
  262. * Environment
  263. */
  264. #define CONFIG_ENV_OVERWRITE
  265. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  266. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  267. /*
  268. * BOOTP options
  269. */
  270. #define CONFIG_BOOTP_BOOTFILESIZE
  271. /* Watchdog */
  272. #undef CONFIG_WATCHDOG /* watchdog disabled */
  273. /*
  274. * Miscellaneous configurable options
  275. */
  276. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  277. #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
  278. /*
  279. * For booting Linux, the board info and command line data
  280. * have to be in the first 256 MB of memory, since this is
  281. * the maximum mapped by the Linux kernel during initialization.
  282. */
  283. /* Initial Memory map for Linux*/
  284. #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
  285. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  286. /*
  287. * System performance
  288. */
  289. #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
  290. #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
  291. #define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */
  292. #define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */
  293. /*
  294. * System IO Config
  295. */
  296. /* Needed for gigabit to work on TSEC 1 */
  297. #define CONFIG_SYS_SICRH SICRH_TSOBI1
  298. /* USB DR as device + USB MPH as host */
  299. #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1)
  300. #if defined(CONFIG_CMD_KGDB)
  301. #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
  302. #endif
  303. /*
  304. * Environment Configuration
  305. */
  306. #define CONFIG_ENV_OVERWRITE
  307. #define CONFIG_NETDEV "eth0"
  308. /* Default path and filenames */
  309. #define CONFIG_ROOTPATH "/nfsroot/rootfs"
  310. #define CONFIG_BOOTFILE "uImage"
  311. /* U-Boot image on TFTP server */
  312. #define CONFIG_UBOOTPATH "u-boot.bin"
  313. #ifdef CONFIG_TARGET_MPC8349ITX
  314. #define CONFIG_FDTFILE "mpc8349emitx.dtb"
  315. #else
  316. #define CONFIG_FDTFILE "mpc8349emitxgp.dtb"
  317. #endif
  318. #define CONFIG_EXTRA_ENV_SETTINGS \
  319. "console=" __stringify(CONSOLE) "\0" \
  320. "netdev=" CONFIG_NETDEV "\0" \
  321. "uboot=" CONFIG_UBOOTPATH "\0" \
  322. "tftpflash=tftpboot $loadaddr $uboot; " \
  323. "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
  324. " +$filesize; " \
  325. "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
  326. " +$filesize; " \
  327. "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  328. " $filesize; " \
  329. "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
  330. " +$filesize; " \
  331. "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  332. " $filesize\0" \
  333. "fdtaddr=780000\0" \
  334. "fdtfile=" CONFIG_FDTFILE "\0"
  335. #define CONFIG_NFSBOOTCOMMAND \
  336. "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \
  337. " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
  338. " console=$console,$baudrate $othbootargs; " \
  339. "tftp $loadaddr $bootfile;" \
  340. "tftp $fdtaddr $fdtfile;" \
  341. "bootm $loadaddr - $fdtaddr"
  342. #define CONFIG_RAMBOOTCOMMAND \
  343. "setenv bootargs root=/dev/ram rw" \
  344. " console=$console,$baudrate $othbootargs; " \
  345. "tftp $ramdiskaddr $ramdiskfile;" \
  346. "tftp $loadaddr $bootfile;" \
  347. "tftp $fdtaddr $fdtfile;" \
  348. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  349. #endif