MPC8323ERDB.h 9.2 KB

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  1. /*
  2. * Copyright (C) 2007 Freescale Semiconductor, Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License version 2 as published
  6. * by the Free Software Foundation.
  7. */
  8. #ifndef __CONFIG_H
  9. #define __CONFIG_H
  10. /*
  11. * High Level Configuration Options
  12. */
  13. #define CONFIG_E300 1 /* E300 family */
  14. /*
  15. * System IO Config
  16. */
  17. #define CONFIG_SYS_SICRL 0x00000000
  18. /*
  19. * DDR Setup
  20. */
  21. #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
  22. #undef CONFIG_SPD_EEPROM
  23. #if defined(CONFIG_SPD_EEPROM)
  24. /* Determine DDR configuration from I2C interface
  25. */
  26. #define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
  27. #else
  28. /* Manually set up DDR parameters
  29. */
  30. #define CONFIG_SYS_DDR_SIZE 64 /* MB */
  31. #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
  32. | CSCONFIG_ROW_BIT_13 \
  33. | CSCONFIG_COL_BIT_9)
  34. /* 0x80010101 */
  35. #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  36. | (0 << TIMING_CFG0_WRT_SHIFT) \
  37. | (0 << TIMING_CFG0_RRT_SHIFT) \
  38. | (0 << TIMING_CFG0_WWT_SHIFT) \
  39. | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  40. | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  41. | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  42. | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  43. /* 0x00220802 */
  44. #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
  45. | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  46. | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
  47. | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  48. | (3 << TIMING_CFG1_REFREC_SHIFT) \
  49. | (2 << TIMING_CFG1_WRREC_SHIFT) \
  50. | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  51. | (2 << TIMING_CFG1_WRTORD_SHIFT))
  52. /* 0x26253222 */
  53. #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
  54. | (31 << TIMING_CFG2_CPO_SHIFT) \
  55. | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  56. | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  57. | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  58. | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  59. | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
  60. /* 0x1f9048c7 */
  61. #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  62. #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  63. /* 0x02000000 */
  64. #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
  65. | (0x0232 << SDRAM_MODE_SD_SHIFT))
  66. /* 0x44480232 */
  67. #define CONFIG_SYS_DDR_MODE2 0x8000c000
  68. #define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
  69. | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  70. /* 0x03200064 */
  71. #define CONFIG_SYS_DDR_CS0_BNDS 0x00000003
  72. #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
  73. | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  74. | SDRAM_CFG_32_BE)
  75. /* 0x43080000 */
  76. #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
  77. #endif
  78. /*
  79. * Memory test
  80. */
  81. #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
  82. #define CONFIG_SYS_MEMTEST_START 0x00030000 /* memtest region */
  83. #define CONFIG_SYS_MEMTEST_END 0x03f00000
  84. /*
  85. * The reserved memory
  86. */
  87. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  88. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  89. #define CONFIG_SYS_RAMBOOT
  90. #else
  91. #undef CONFIG_SYS_RAMBOOT
  92. #endif
  93. /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
  94. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
  95. #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
  96. /*
  97. * Initial RAM Base Address Setup
  98. */
  99. #define CONFIG_SYS_INIT_RAM_LOCK 1
  100. #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
  101. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
  102. #define CONFIG_SYS_GBL_DATA_OFFSET \
  103. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  104. /*
  105. * FLASH on the Local Bus
  106. */
  107. #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
  108. #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
  109. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  110. #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
  111. #undef CONFIG_SYS_FLASH_CHECKSUM
  112. /*
  113. * Serial Port
  114. */
  115. #define CONFIG_SYS_NS16550_SERIAL
  116. #define CONFIG_SYS_NS16550_REG_SIZE 1
  117. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  118. #define CONFIG_SYS_BAUDRATE_TABLE \
  119. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  120. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
  121. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
  122. /* I2C */
  123. #define CONFIG_SYS_I2C
  124. #define CONFIG_SYS_I2C_FSL
  125. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  126. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  127. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  128. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
  129. /*
  130. * Config on-board EEPROM
  131. */
  132. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
  133. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  134. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
  135. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
  136. /*
  137. * General PCI
  138. * Addresses are mapped 1-1.
  139. */
  140. #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
  141. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  142. #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
  143. #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
  144. #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
  145. #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
  146. #define CONFIG_SYS_PCI1_IO_BASE 0xd0000000
  147. #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
  148. #define CONFIG_SYS_PCI1_IO_SIZE 0x04000000 /* 64M */
  149. #ifdef CONFIG_PCI
  150. #define CONFIG_PCI_INDIRECT_BRIDGE
  151. #define CONFIG_PCI_SKIP_HOST_BRIDGE
  152. #undef CONFIG_EEPRO100
  153. #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  154. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
  155. #endif /* CONFIG_PCI */
  156. /*
  157. * QE UEC ethernet configuration
  158. */
  159. #define CONFIG_UEC_ETH
  160. #define CONFIG_ETHPRIME "UEC0"
  161. #define CONFIG_UEC_ETH1 /* ETH3 */
  162. #ifdef CONFIG_UEC_ETH1
  163. #define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */
  164. #define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
  165. #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
  166. #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
  167. #define CONFIG_SYS_UEC1_PHY_ADDR 4
  168. #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
  169. #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
  170. #endif
  171. #define CONFIG_UEC_ETH2 /* ETH4 */
  172. #ifdef CONFIG_UEC_ETH2
  173. #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
  174. #define CONFIG_SYS_UEC2_RX_CLK QE_CLK16
  175. #define CONFIG_SYS_UEC2_TX_CLK QE_CLK3
  176. #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
  177. #define CONFIG_SYS_UEC2_PHY_ADDR 0
  178. #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
  179. #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
  180. #endif
  181. /*
  182. * Environment
  183. */
  184. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  185. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  186. /*
  187. * BOOTP options
  188. */
  189. #define CONFIG_BOOTP_BOOTFILESIZE
  190. /*
  191. * Command line configuration.
  192. */
  193. #undef CONFIG_WATCHDOG /* watchdog disabled */
  194. /*
  195. * Miscellaneous configurable options
  196. */
  197. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  198. /*
  199. * For booting Linux, the board info and command line data
  200. * have to be in the first 256 MB of memory, since this is
  201. * the maximum mapped by the Linux kernel during initialization.
  202. */
  203. /* Initial Memory map for Linux */
  204. #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
  205. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  206. #if (CONFIG_CMD_KGDB)
  207. #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
  208. #endif
  209. /*
  210. * Environment Configuration
  211. */
  212. #define CONFIG_ENV_OVERWRITE
  213. #define CONFIG_HAS_ETH0 /* add support for "ethaddr" */
  214. #define CONFIG_HAS_ETH1 /* add support for "eth1addr" */
  215. /* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM
  216. * (see CONFIG_SYS_I2C_EEPROM) */
  217. /* MAC address offset in I2C EEPROM */
  218. #define CONFIG_SYS_I2C_MAC_OFFSET 0x7f00
  219. #define CONFIG_NETDEV "eth1"
  220. #define CONFIG_HOSTNAME "mpc8323erdb"
  221. #define CONFIG_ROOTPATH "/nfsroot"
  222. #define CONFIG_BOOTFILE "uImage"
  223. /* U-Boot image on TFTP server */
  224. #define CONFIG_UBOOTPATH "u-boot.bin"
  225. #define CONFIG_FDTFILE "mpc832x_rdb.dtb"
  226. #define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot"
  227. /* default location for tftp and bootm */
  228. #define CONFIG_LOADADDR 800000
  229. #define CONFIG_EXTRA_ENV_SETTINGS \
  230. "netdev=" CONFIG_NETDEV "\0" \
  231. "uboot=" CONFIG_UBOOTPATH "\0" \
  232. "tftpflash=tftp $loadaddr $uboot;" \
  233. "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
  234. " +$filesize; " \
  235. "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
  236. " +$filesize; " \
  237. "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  238. " $filesize; " \
  239. "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
  240. " +$filesize; " \
  241. "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  242. " $filesize\0" \
  243. "fdtaddr=780000\0" \
  244. "fdtfile=" CONFIG_FDTFILE "\0" \
  245. "ramdiskaddr=1000000\0" \
  246. "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \
  247. "console=ttyS0\0" \
  248. "setbootargs=setenv bootargs " \
  249. "root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
  250. "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
  251. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
  252. "$netdev:off "\
  253. "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
  254. #define CONFIG_NFSBOOTCOMMAND \
  255. "setenv rootdev /dev/nfs;" \
  256. "run setbootargs;" \
  257. "run setipargs;" \
  258. "tftp $loadaddr $bootfile;" \
  259. "tftp $fdtaddr $fdtfile;" \
  260. "bootm $loadaddr - $fdtaddr"
  261. #define CONFIG_RAMBOOTCOMMAND \
  262. "setenv rootdev /dev/ram;" \
  263. "run setbootargs;" \
  264. "tftp $ramdiskaddr $ramdiskfile;" \
  265. "tftp $loadaddr $bootfile;" \
  266. "tftp $fdtaddr $fdtfile;" \
  267. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  268. #endif /* __CONFIG_H */