MPC8315ERDB.h 11 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
  4. *
  5. * Dave Liu <daveliu@freescale.com>
  6. */
  7. #ifndef __CONFIG_H
  8. #define __CONFIG_H
  9. #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
  10. #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
  11. #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
  12. #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
  13. #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
  14. #ifndef CONFIG_SYS_MONITOR_BASE
  15. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  16. #endif
  17. /*
  18. * High Level Configuration Options
  19. */
  20. #define CONFIG_E300 1 /* E300 family */
  21. /*
  22. * System IO Config
  23. */
  24. #define CONFIG_SYS_SICRH 0x00000000
  25. #define CONFIG_SYS_SICRL 0x00000000 /* 3.3V, no delay */
  26. #define CONFIG_HWCONFIG
  27. /*
  28. * DDR Setup
  29. */
  30. #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
  31. #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  32. #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
  33. | DDRCDR_PZ_LOZ \
  34. | DDRCDR_NZ_LOZ \
  35. | DDRCDR_ODT \
  36. | DDRCDR_Q_DRN)
  37. /* 0x7b880001 */
  38. /*
  39. * Manually set up DDR parameters
  40. * consist of two chips HY5PS12621BFP-C4 from HYNIX
  41. */
  42. #define CONFIG_SYS_DDR_SIZE 128 /* MB */
  43. #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
  44. #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
  45. | CSCONFIG_ODT_RD_NEVER \
  46. | CSCONFIG_ODT_WR_ONLY_CURRENT \
  47. | CSCONFIG_ROW_BIT_13 \
  48. | CSCONFIG_COL_BIT_10)
  49. /* 0x80010102 */
  50. #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  51. #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  52. | (0 << TIMING_CFG0_WRT_SHIFT) \
  53. | (0 << TIMING_CFG0_RRT_SHIFT) \
  54. | (0 << TIMING_CFG0_WWT_SHIFT) \
  55. | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  56. | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  57. | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  58. | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  59. /* 0x00220802 */
  60. #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
  61. | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  62. | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
  63. | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  64. | (6 << TIMING_CFG1_REFREC_SHIFT) \
  65. | (2 << TIMING_CFG1_WRREC_SHIFT) \
  66. | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  67. | (2 << TIMING_CFG1_WRTORD_SHIFT))
  68. /* 0x27256222 */
  69. #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
  70. | (4 << TIMING_CFG2_CPO_SHIFT) \
  71. | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  72. | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  73. | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  74. | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  75. | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
  76. /* 0x121048c5 */
  77. #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
  78. | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  79. /* 0x03600100 */
  80. #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
  81. | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  82. | SDRAM_CFG_DBW_32)
  83. /* 0x43080000 */
  84. #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
  85. #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
  86. | (0x0232 << SDRAM_MODE_SD_SHIFT))
  87. /* ODT 150ohm CL=3, AL=1 on SDRAM */
  88. #define CONFIG_SYS_DDR_MODE2 0x00000000
  89. /*
  90. * Memory test
  91. */
  92. #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
  93. #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
  94. #define CONFIG_SYS_MEMTEST_END 0x00140000
  95. /*
  96. * The reserved memory
  97. */
  98. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
  99. #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
  100. /*
  101. * Initial RAM Base Address Setup
  102. */
  103. #define CONFIG_SYS_INIT_RAM_LOCK 1
  104. #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
  105. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
  106. #define CONFIG_SYS_GBL_DATA_OFFSET \
  107. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  108. #define CONFIG_FSL_ELBC
  109. /*
  110. * FLASH on the Local Bus
  111. */
  112. #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  113. #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
  114. #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */
  115. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  116. /* 127 64KB sectors and 8 8KB top sectors per device */
  117. #define CONFIG_SYS_MAX_FLASH_SECT 135
  118. #undef CONFIG_SYS_FLASH_CHECKSUM
  119. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  120. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  121. /*
  122. * NAND Flash on the Local Bus
  123. */
  124. #ifdef CONFIG_NAND_SPL
  125. #define CONFIG_SYS_NAND_BASE 0xFFF00000
  126. #else
  127. #define CONFIG_SYS_NAND_BASE 0xE0600000
  128. #endif
  129. #define CONFIG_MTD_PARTITION
  130. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  131. #define CONFIG_NAND_FSL_ELBC 1
  132. #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
  133. #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */
  134. #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
  135. #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
  136. #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
  137. #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
  138. #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
  139. /* Still needed for spl_minimal.c */
  140. #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
  141. #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
  142. #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
  143. !defined(CONFIG_NAND_SPL)
  144. #define CONFIG_SYS_RAMBOOT
  145. #else
  146. #undef CONFIG_SYS_RAMBOOT
  147. #endif
  148. /*
  149. * Serial Port
  150. */
  151. #define CONFIG_SYS_NS16550_SERIAL
  152. #define CONFIG_SYS_NS16550_REG_SIZE 1
  153. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
  154. #define CONFIG_SYS_BAUDRATE_TABLE \
  155. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  156. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
  157. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
  158. /* I2C */
  159. #define CONFIG_SYS_I2C
  160. #define CONFIG_SYS_I2C_FSL
  161. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  162. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  163. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  164. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
  165. /*
  166. * Board info - revision and where boot from
  167. */
  168. #define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39
  169. /*
  170. * Config on-board RTC
  171. */
  172. #define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */
  173. #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
  174. /*
  175. * General PCI
  176. * Addresses are mapped 1-1.
  177. */
  178. #define CONFIG_SYS_PCI_MEM_BASE 0x80000000
  179. #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
  180. #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
  181. #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
  182. #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
  183. #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
  184. #define CONFIG_SYS_PCI_IO_BASE 0x00000000
  185. #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
  186. #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
  187. #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
  188. #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
  189. #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
  190. #define CONFIG_SYS_PCIE1_BASE 0xA0000000
  191. #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
  192. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
  193. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
  194. #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
  195. #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
  196. #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
  197. #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
  198. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
  199. #define CONFIG_SYS_PCIE2_BASE 0xC0000000
  200. #define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000
  201. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000
  202. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
  203. #define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000
  204. #define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000
  205. #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
  206. #define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000
  207. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
  208. #define CONFIG_PCI_INDIRECT_BRIDGE
  209. #define CONFIG_PCIE
  210. #define CONFIG_EEPRO100
  211. #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  212. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
  213. #define CONFIG_HAS_FSL_DR_USB
  214. #define CONFIG_SYS_SCCR_USBDRCM 3
  215. #define CONFIG_USB_EHCI_FSL
  216. #define CONFIG_USB_PHY_TYPE "utmi"
  217. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  218. /*
  219. * TSEC
  220. */
  221. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  222. #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
  223. #define CONFIG_SYS_TSEC2_OFFSET 0x25000
  224. #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
  225. /*
  226. * TSEC ethernet configuration
  227. */
  228. #define CONFIG_TSEC1 1
  229. #define CONFIG_TSEC1_NAME "eTSEC0"
  230. #define CONFIG_TSEC2 1
  231. #define CONFIG_TSEC2_NAME "eTSEC1"
  232. #define TSEC1_PHY_ADDR 0
  233. #define TSEC2_PHY_ADDR 1
  234. #define TSEC1_PHYIDX 0
  235. #define TSEC2_PHYIDX 0
  236. #define TSEC1_FLAGS TSEC_GIGABIT
  237. #define TSEC2_FLAGS TSEC_GIGABIT
  238. /* Options are: eTSEC[0-1] */
  239. #define CONFIG_ETHPRIME "eTSEC1"
  240. /*
  241. * SATA
  242. */
  243. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  244. #define CONFIG_SATA1
  245. #define CONFIG_SYS_SATA1_OFFSET 0x18000
  246. #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
  247. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  248. #define CONFIG_SATA2
  249. #define CONFIG_SYS_SATA2_OFFSET 0x19000
  250. #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
  251. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  252. #ifdef CONFIG_FSL_SATA
  253. #define CONFIG_LBA48
  254. #endif
  255. /*
  256. * Environment
  257. */
  258. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  259. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  260. /*
  261. * BOOTP options
  262. */
  263. #define CONFIG_BOOTP_BOOTFILESIZE
  264. /*
  265. * Command line configuration.
  266. */
  267. #undef CONFIG_WATCHDOG /* watchdog disabled */
  268. /*
  269. * Miscellaneous configurable options
  270. */
  271. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  272. /*
  273. * For booting Linux, the board info and command line data
  274. * have to be in the first 256 MB of memory, since this is
  275. * the maximum mapped by the Linux kernel during initialization.
  276. */
  277. #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
  278. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  279. /*
  280. * MMU Setup
  281. */
  282. #if defined(CONFIG_CMD_KGDB)
  283. #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
  284. #endif
  285. /*
  286. * Environment Configuration
  287. */
  288. #define CONFIG_ENV_OVERWRITE
  289. #if defined(CONFIG_TSEC_ENET)
  290. #define CONFIG_HAS_ETH0
  291. #define CONFIG_HAS_ETH1
  292. #endif
  293. #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
  294. #define CONFIG_EXTRA_ENV_SETTINGS \
  295. "netdev=eth0\0" \
  296. "consoledev=ttyS0\0" \
  297. "ramdiskaddr=1000000\0" \
  298. "ramdiskfile=ramfs.83xx\0" \
  299. "fdtaddr=780000\0" \
  300. "fdtfile=mpc8315erdb.dtb\0" \
  301. "usb_phy_type=utmi\0" \
  302. ""
  303. #define CONFIG_NFSBOOTCOMMAND \
  304. "setenv bootargs root=/dev/nfs rw " \
  305. "nfsroot=$serverip:$rootpath " \
  306. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
  307. "$netdev:off " \
  308. "console=$consoledev,$baudrate $othbootargs;" \
  309. "tftp $loadaddr $bootfile;" \
  310. "tftp $fdtaddr $fdtfile;" \
  311. "bootm $loadaddr - $fdtaddr"
  312. #define CONFIG_RAMBOOTCOMMAND \
  313. "setenv bootargs root=/dev/ram rw " \
  314. "console=$consoledev,$baudrate $othbootargs;" \
  315. "tftp $ramdiskaddr $ramdiskfile;" \
  316. "tftp $loadaddr $bootfile;" \
  317. "tftp $fdtaddr $fdtfile;" \
  318. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  319. #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
  320. #endif /* __CONFIG_H */