MPC8308RDB.h 9.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
  4. * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
  5. *
  6. */
  7. #ifndef __CONFIG_H
  8. #define __CONFIG_H
  9. /*
  10. * High Level Configuration Options
  11. */
  12. #define CONFIG_E300 1 /* E300 family */
  13. #ifdef CONFIG_MMC
  14. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
  15. #define CONFIG_SYS_FSL_ESDHC_USE_PIO
  16. #endif
  17. /*
  18. * On-board devices
  19. *
  20. * TSEC1 is SoC TSEC
  21. * TSEC2 is VSC switch
  22. */
  23. #define CONFIG_TSEC1
  24. #define CONFIG_VSC7385_ENET
  25. /*
  26. * SERDES
  27. */
  28. #define CONFIG_FSL_SERDES
  29. #define CONFIG_FSL_SERDES1 0xe3000
  30. /*
  31. * DDR Setup
  32. */
  33. #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
  34. #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  35. #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
  36. | DDRCDR_PZ_LOZ \
  37. | DDRCDR_NZ_LOZ \
  38. | DDRCDR_ODT \
  39. | DDRCDR_Q_DRN)
  40. /* 0x7b880001 */
  41. /*
  42. * Manually set up DDR parameters
  43. * consist of two chips HY5PS12621BFP-C4 from HYNIX
  44. */
  45. #define CONFIG_SYS_DDR_SIZE 128 /* MB */
  46. #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
  47. #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
  48. | CSCONFIG_ODT_RD_NEVER \
  49. | CSCONFIG_ODT_WR_ONLY_CURRENT \
  50. | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
  51. /* 0x80010102 */
  52. #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  53. #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  54. | (0 << TIMING_CFG0_WRT_SHIFT) \
  55. | (0 << TIMING_CFG0_RRT_SHIFT) \
  56. | (0 << TIMING_CFG0_WWT_SHIFT) \
  57. | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  58. | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  59. | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  60. | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  61. /* 0x00220802 */
  62. #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
  63. | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  64. | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
  65. | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  66. | (6 << TIMING_CFG1_REFREC_SHIFT) \
  67. | (2 << TIMING_CFG1_WRREC_SHIFT) \
  68. | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  69. | (2 << TIMING_CFG1_WRTORD_SHIFT))
  70. /* 0x27256222 */
  71. #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
  72. | (4 << TIMING_CFG2_CPO_SHIFT) \
  73. | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  74. | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  75. | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  76. | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  77. | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
  78. /* 0x121048c5 */
  79. #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
  80. | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  81. /* 0x03600100 */
  82. #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
  83. | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  84. | SDRAM_CFG_DBW_32)
  85. /* 0x43080000 */
  86. #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
  87. #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
  88. | (0x0232 << SDRAM_MODE_SD_SHIFT))
  89. /* ODT 150ohm CL=3, AL=1 on SDRAM */
  90. #define CONFIG_SYS_DDR_MODE2 0x00000000
  91. /*
  92. * Memory test
  93. */
  94. #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
  95. #define CONFIG_SYS_MEMTEST_END 0x07f00000
  96. /*
  97. * The reserved memory
  98. */
  99. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  100. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
  101. #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
  102. /*
  103. * Initial RAM Base Address Setup
  104. */
  105. #define CONFIG_SYS_INIT_RAM_LOCK 1
  106. #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
  107. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
  108. #define CONFIG_SYS_GBL_DATA_OFFSET \
  109. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  110. /*
  111. * FLASH on the Local Bus
  112. */
  113. #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  114. #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
  115. #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */
  116. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  117. /* 127 64KB sectors and 8 8KB top sectors per device */
  118. #define CONFIG_SYS_MAX_FLASH_SECT 135
  119. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  120. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  121. /*
  122. * NAND Flash on the Local Bus
  123. */
  124. #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
  125. #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */
  126. /* 0xFFFF8396 */
  127. #ifdef CONFIG_VSC7385_ENET
  128. #define CONFIG_TSEC2
  129. /* VSC7385 Base address on CS2 */
  130. #define CONFIG_SYS_VSC7385_BASE 0xF0000000
  131. #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
  132. /* 0xFFFE09FF */
  133. /* The flash address and size of the VSC7385 firmware image */
  134. #define CONFIG_VSC7385_IMAGE 0xFE7FE000
  135. #define CONFIG_VSC7385_IMAGE_SIZE 8192
  136. #endif
  137. /*
  138. * Serial Port
  139. */
  140. #define CONFIG_SYS_NS16550_SERIAL
  141. #define CONFIG_SYS_NS16550_REG_SIZE 1
  142. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  143. #define CONFIG_SYS_BAUDRATE_TABLE \
  144. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  145. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
  146. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
  147. /* I2C */
  148. #define CONFIG_SYS_I2C
  149. #define CONFIG_SYS_I2C_FSL
  150. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  151. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  152. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  153. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  154. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  155. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  156. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
  157. /*
  158. * SPI on header J8
  159. *
  160. * WARNING: enabling this will break TSEC2 (connected to the Vitesse switch)
  161. * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins.
  162. */
  163. #ifdef CONFIG_MPC8XXX_SPI
  164. #define CONFIG_USE_SPIFLASH
  165. #endif
  166. /*
  167. * Board info - revision and where boot from
  168. */
  169. #define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39
  170. /*
  171. * Config on-board RTC
  172. */
  173. #define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */
  174. #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
  175. /*
  176. * General PCI
  177. * Addresses are mapped 1-1.
  178. */
  179. #define CONFIG_SYS_PCIE1_BASE 0xA0000000
  180. #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
  181. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
  182. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
  183. #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
  184. #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
  185. #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
  186. #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
  187. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
  188. /* enable PCIE clock */
  189. #define CONFIG_SYS_SCCR_PCIEXP1CM 1
  190. #define CONFIG_PCI_INDIRECT_BRIDGE
  191. #define CONFIG_PCIE
  192. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
  193. #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
  194. /*
  195. * TSEC
  196. */
  197. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  198. #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
  199. #define CONFIG_SYS_TSEC2_OFFSET 0x25000
  200. #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
  201. /*
  202. * TSEC ethernet configuration
  203. */
  204. #define CONFIG_TSEC1_NAME "eTSEC0"
  205. #define CONFIG_TSEC2_NAME "eTSEC1"
  206. #define TSEC1_PHY_ADDR 2
  207. #define TSEC2_PHY_ADDR 1
  208. #define TSEC1_PHYIDX 0
  209. #define TSEC2_PHYIDX 0
  210. #define TSEC1_FLAGS TSEC_GIGABIT
  211. #define TSEC2_FLAGS TSEC_GIGABIT
  212. /* Options are: eTSEC[0-1] */
  213. #define CONFIG_ETHPRIME "eTSEC0"
  214. /*
  215. * Environment
  216. */
  217. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  218. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  219. /*
  220. * BOOTP options
  221. */
  222. #define CONFIG_BOOTP_BOOTFILESIZE
  223. /*
  224. * Command line configuration.
  225. */
  226. /*
  227. * Miscellaneous configurable options
  228. */
  229. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  230. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  231. /* Boot Argument Buffer Size */
  232. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  233. /*
  234. * For booting Linux, the board info and command line data
  235. * have to be in the first 256 MB of memory, since this is
  236. * the maximum mapped by the Linux kernel during initialization.
  237. */
  238. #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
  239. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  240. /*
  241. * Environment Configuration
  242. */
  243. #define CONFIG_ENV_OVERWRITE
  244. #if defined(CONFIG_TSEC_ENET)
  245. #define CONFIG_HAS_ETH0
  246. #define CONFIG_HAS_ETH1
  247. #endif
  248. #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
  249. #define CONFIG_EXTRA_ENV_SETTINGS \
  250. "netdev=eth0\0" \
  251. "consoledev=ttyS0\0" \
  252. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  253. "nfsroot=${serverip}:${rootpath}\0" \
  254. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  255. "addip=setenv bootargs ${bootargs} " \
  256. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  257. ":${hostname}:${netdev}:off panic=1\0" \
  258. "addtty=setenv bootargs ${bootargs}" \
  259. " console=${consoledev},${baudrate}\0" \
  260. "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
  261. "addmisc=setenv bootargs ${bootargs}\0" \
  262. "kernel_addr=FE080000\0" \
  263. "fdt_addr=FE280000\0" \
  264. "ramdisk_addr=FE290000\0" \
  265. "u-boot=mpc8308rdb/u-boot.bin\0" \
  266. "kernel_addr_r=1000000\0" \
  267. "fdt_addr_r=C00000\0" \
  268. "hostname=mpc8308rdb\0" \
  269. "bootfile=mpc8308rdb/uImage\0" \
  270. "fdtfile=mpc8308rdb/mpc8308rdb.dtb\0" \
  271. "rootpath=/opt/eldk-4.2/ppc_6xx\0" \
  272. "flash_self=run ramargs addip addtty addmtd addmisc;" \
  273. "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
  274. "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
  275. "bootm ${kernel_addr} - ${fdt_addr}\0" \
  276. "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
  277. "tftp ${fdt_addr_r} ${fdtfile};" \
  278. "run nfsargs addip addtty addmtd addmisc;" \
  279. "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
  280. "bootcmd=run flash_self\0" \
  281. "load=tftp ${loadaddr} ${u-boot}\0" \
  282. "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
  283. " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
  284. " +${filesize};cp.b ${fileaddr} " \
  285. __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
  286. "upd=run load update\0" \
  287. #endif /* __CONFIG_H */