M5475EVB.h 7.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Configuation settings for the Freescale MCF5475 board.
  4. *
  5. * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
  6. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  7. */
  8. /*
  9. * board/config.h - configuration options, board specific
  10. */
  11. #ifndef _M5475EVB_H
  12. #define _M5475EVB_H
  13. /*
  14. * High Level Configuration Options
  15. * (easy to change)
  16. */
  17. #define CONFIG_MCFUART
  18. #define CONFIG_SYS_UART_PORT (0)
  19. #undef CONFIG_HW_WATCHDOG
  20. #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
  21. #define CONFIG_SLTTMR
  22. #define CONFIG_FSLDMAFEC
  23. #ifdef CONFIG_FSLDMAFEC
  24. # define CONFIG_MII_INIT 1
  25. # define CONFIG_HAS_ETH1
  26. # define CONFIG_SYS_DMA_USE_INTSRAM 1
  27. # define CONFIG_SYS_DISCOVER_PHY
  28. # define CONFIG_SYS_RX_ETH_BUFFER 32
  29. # define CONFIG_SYS_TX_ETH_BUFFER 48
  30. # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  31. # define CONFIG_SYS_FEC0_PINMUX 0
  32. # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
  33. # define CONFIG_SYS_FEC1_PINMUX 0
  34. # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE
  35. # define MCFFEC_TOUT_LOOP 50000
  36. /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  37. # ifndef CONFIG_SYS_DISCOVER_PHY
  38. # define FECDUPLEX FULL
  39. # define FECSPEED _100BASET
  40. # else
  41. # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  42. # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  43. # endif
  44. # endif /* CONFIG_SYS_DISCOVER_PHY */
  45. # define CONFIG_IPADDR 192.162.1.2
  46. # define CONFIG_NETMASK 255.255.255.0
  47. # define CONFIG_SERVERIP 192.162.1.1
  48. # define CONFIG_GATEWAYIP 192.162.1.1
  49. #endif
  50. #ifdef CONFIG_CMD_USB
  51. # define CONFIG_USB_OHCI_NEW
  52. # define CONFIG_PCI_OHCI
  53. # undef CONFIG_SYS_USB_OHCI_BOARD_INIT
  54. # undef CONFIG_SYS_USB_OHCI_CPU_INIT
  55. # define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
  56. # define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561"
  57. # define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
  58. #endif
  59. /* I2C */
  60. #define CONFIG_SYS_I2C
  61. #define CONFIG_SYS_I2C_FSL
  62. #define CONFIG_SYS_FSL_I2C_SPEED 80000
  63. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  64. #define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00
  65. #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
  66. /* PCI */
  67. #ifdef CONFIG_CMD_PCI
  68. #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
  69. #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
  70. #define CONFIG_SYS_PCI_MEM_BUS 0x80000000
  71. #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
  72. #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
  73. #define CONFIG_SYS_PCI_IO_BUS 0x71000000
  74. #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS
  75. #define CONFIG_SYS_PCI_IO_SIZE 0x01000000
  76. #define CONFIG_SYS_PCI_CFG_BUS 0x70000000
  77. #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
  78. #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
  79. #endif
  80. #define CONFIG_UDP_CHECKSUM
  81. #ifdef CONFIG_MCFFEC
  82. # define CONFIG_IPADDR 192.162.1.2
  83. # define CONFIG_NETMASK 255.255.255.0
  84. # define CONFIG_SERVERIP 192.162.1.1
  85. # define CONFIG_GATEWAYIP 192.162.1.1
  86. #endif /* FEC_ENET */
  87. #define CONFIG_HOSTNAME "M547xEVB"
  88. #define CONFIG_EXTRA_ENV_SETTINGS \
  89. "netdev=eth0\0" \
  90. "loadaddr=10000\0" \
  91. "u-boot=u-boot.bin\0" \
  92. "load=tftp ${loadaddr) ${u-boot}\0" \
  93. "upd=run load; run prog\0" \
  94. "prog=prot off bank 1;" \
  95. "era ff800000 ff83ffff;" \
  96. "cp.b ${loadaddr} ff800000 ${filesize};"\
  97. "save\0" \
  98. ""
  99. #define CONFIG_PRAM 512 /* 512 KB */
  100. #define CONFIG_SYS_LOAD_ADDR 0x00010000
  101. #define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK
  102. #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
  103. #define CONFIG_SYS_MBAR 0xF0000000
  104. #define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000)
  105. #define CONFIG_SYS_INTSRAMSZ 0x8000
  106. /*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/
  107. /*
  108. * Low Level Configuration Settings
  109. * (address mappings, register initial values, etc.)
  110. * You should know what you are doing if you make changes here.
  111. */
  112. /*-----------------------------------------------------------------------
  113. * Definitions for initial stack pointer and data area (in DPRAM)
  114. */
  115. #define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000
  116. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
  117. #define CONFIG_SYS_INIT_RAM_CTRL 0x21
  118. #define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
  119. #define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */
  120. #define CONFIG_SYS_INIT_RAM1_CTRL 0x21
  121. #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
  122. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  123. /*-----------------------------------------------------------------------
  124. * Start addresses for the final memory configuration
  125. * (Set up by the startup code)
  126. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  127. */
  128. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  129. #define CONFIG_SYS_SDRAM_CFG1 0x73711630
  130. #define CONFIG_SYS_SDRAM_CFG2 0x46770000
  131. #define CONFIG_SYS_SDRAM_CTRL 0xE10B0000
  132. #define CONFIG_SYS_SDRAM_EMOD 0x40010000
  133. #define CONFIG_SYS_SDRAM_MODE 0x018D0000
  134. #define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA
  135. #ifdef CONFIG_SYS_DRAMSZ1
  136. # define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1)
  137. #else
  138. # define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ
  139. #endif
  140. #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
  141. #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
  142. #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
  143. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  144. #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
  145. /* Reserve 256 kB for malloc() */
  146. #define CONFIG_SYS_MALLOC_LEN (256 << 10)
  147. /*
  148. * For booting Linux, the board info and command line data
  149. * have to be in the first 8 MB of memory, since this is
  150. * the maximum mapped by the Linux kernel during initialization ??
  151. */
  152. #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
  153. /*-----------------------------------------------------------------------
  154. * FLASH organization
  155. */
  156. #ifdef CONFIG_SYS_FLASH_CFI
  157. # define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
  158. # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  159. # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
  160. #ifdef CONFIG_SYS_NOR1SZ
  161. # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
  162. # define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20)
  163. # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
  164. #else
  165. # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  166. # define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20)
  167. #endif
  168. #endif
  169. /* Configuration for environment
  170. * Environment is not embedded in u-boot but at offset 0x40000 on the flash.
  171. * First time runing may have env crc error warning if there is
  172. * no correct environment on the flash.
  173. */
  174. /*-----------------------------------------------------------------------
  175. * Cache Configuration
  176. */
  177. #define CONFIG_SYS_CACHELINE_SIZE 16
  178. #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  179. CONFIG_SYS_INIT_RAM_SIZE - 8)
  180. #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  181. CONFIG_SYS_INIT_RAM_SIZE - 4)
  182. #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \
  183. CF_CACR_IDCM)
  184. #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
  185. #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
  186. CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
  187. CF_ACR_EN | CF_ACR_SM_ALL)
  188. #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \
  189. CF_CACR_IEC | CF_CACR_ICINVA)
  190. #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
  191. CF_CACR_DEC | CF_CACR_DDCM_P | \
  192. CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
  193. /*-----------------------------------------------------------------------
  194. * Chipselect bank definitions
  195. */
  196. /*
  197. * CS0 - NOR Flash 1, 2, 4, or 8MB
  198. * CS1 - NOR Flash
  199. * CS2 - Available
  200. * CS3 - Available
  201. * CS4 - Available
  202. * CS5 - Available
  203. */
  204. #define CONFIG_SYS_CS0_BASE 0xFF800000
  205. #define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001)
  206. #define CONFIG_SYS_CS0_CTRL 0x00101980
  207. #ifdef CONFIG_SYS_NOR1SZ
  208. #define CONFIG_SYS_CS1_BASE 0xE0000000
  209. #define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001)
  210. #define CONFIG_SYS_CS1_CTRL 0x00101D80
  211. #endif
  212. #endif /* _M5475EVB_H */